Phase, Clkin Eclkin Reset | Motorola TMS320C6711D manual

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

RESET TIMING (CONTINUED)

Phase 1		Phase 2
				Phase 3

CLKIN

ECLKIN

1

RESET

2

Internal Reset

Internal SYSCLK1

Internal SYSCLK2

Internal SYSCLK3

ECLKOUT	3	4
ECLKOUT
	5	6
CLKOUT2
CLKOUT3	7	8
CLKOUT3
EMIF Z Group†	9	2
EMIF Z Group†
EMIF Low Group†	10	2
EMIF Low Group†
Z Group†	11	2
Z Group†
	12
Z Group 2†		14
Boot and Device		13
Configuration Pins‡
†EMIF Z group consists of:	EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE/SDCAS/SSADS, AWE/SDWE/SSWE, AOE/SDRAS/SSOE and
	HOLDA
EMIF low group consists of: BUSREQ
Z group 1 consists of:	CLKR0, CLKR1, CLKX0, CLKX1, FSR0, FSR1, FSX0, FSX1, DX0, DX1, TOUT0, and TOUT1.
Z group 2 consists of:	All other HPI and GPIO signals

‡Boot and device configurations consist of: HD[8, 4:3].

Figure 40. Reset Timing

Reset Phase 1: The RESET pin is asserted. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.

Reset Phase 2: The RESET pin is deasserted but the internal reset is stretched. During this time, all internal clocks are running at the CLKIN frequency divide-by-8. The CPU is also running at the CLKIN frequency divide-by-8.

Reset Phase 3: Both the RESET pin and internal reset are deasserted. During this time, all internal clocks are running at their default divide-down frequency of CLKIN. The CPU clock (SYSCLK1) is running at CLKIN frequency. The peripheral clock (SYSCLK2) is running at CLKIN frequency divide-by-2. The EMIF internal clock source (SYSCLK3) is running at CLKIN frequency divide-by-2. SYSCLK3 is reflected on the ECLKOUT pin (when EKSRC bit = 0 [default]). CLKOUT3 is running at CLKIN frequency divide-by-8.

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Image 85

Motorola TMS320C6711D warranty Phase, Clkin Eclkin Reset, Emif Z Group† Emif Low Group† Group 2† Boot and Device

Contents

SPRS292A − October 2005 − Revised November Table of Contents Pages ADDITIONS/CHANGES/DELETIONS Revision HistoryMultichannel Buffered Serial Port Timing GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES† GDP and ZDP BGA packages bottom viewBottom View Description Characteristics of the C6711D Processor Device characteristicsHardware Features Internal Clock C6711D Device compatibility Digital Signal Processor Functional block and CPU DSP core diagram CPU DSP core description DA1 ST1DA2 ST2 TMS320C6711D Memory Map Summary Memory map summaryMemory Block Description Block Size Bytes HEX Address Range Emif Registers Peripheral register descriptionsL2 Cache Registers HEX Address Range Acronym Register Name Device Registers Interrupt Selector RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name Comments Quick DMA Qdma and Pseudo Registers† Edma Registers Gpio Registers PLL Controller RegistersHPI Registers HEX Address Range Acronym Register Name Comments Timer Timer 0 and Timer 1 RegistersMcBSP0 and McBSP1 Registers McBSP0 McBSP1 Signal groups description CE2 CE3CE1 CE0 GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 GpioCLKOUT2/GP2 General-Purpose Input/Output Gpio Port Device configurations at device reset Device Configurations BOOTMODE‡ Configuration GDP/ZDP Functional Description PINCLKMODE0 Eksrc Devcfg register descriptionBIT # Name Description Terminal Functions Terminal Functions PIN SignalIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and Interrupts Used for transfer of data, address, and control IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPILittle Endian HD12 Decoded from the two lowest bits of the internal address Only one asserted during any external data accessEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0 RSV IPU RSVRSV IPD Dvdd Name GDP ZDP Supply Voltage PinsCvdd Supply voltage See Note Ground Pins Description Name GDP ZDP Supply Voltage PinsVSS GND VSS PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS GND Description Name GDP ZDP Ground Pins Software Development Tools Development supportHardware Development Tools Device and development-support tool nomenclature Device supportFully qualified production device Prefix Device Family Temperature Range Default 0 C to 90 CDevice Speed Range Technology Documentation support Revision ID CPU CSR register descriptionPwrd PCC DCC Pgie GIE CPU ID CPU CSR Register Bit Field DescriptionPCC Ccfg Register Bit Field Description Cache configuration Ccfg register descriptionL2MODE Interrupt sources and interrupt selector DSP Interrupt Default Selector Module ControlDSP Interrupts Interrupt Selector Event Edma Channels Edma module and Edma selectorEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04 PLL and PLL controller Clkout Signals, Default Settings, and Control PLL Lock and Reset TimesEnabled or Disabled MIN TYP MAX Unit PLL Clock Frequency Ranges†‡ Clock SignalGDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100 PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110 DxEN Oscillator Divider 1 Register OSCDIV1 OSCDIV1 Register 0x01B7 C124OD1EN GP7 GP6 GP5 GP4 GP2 General-purpose input/output GpioDIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR Register Characteristics of the Power-Down Modes Power-supply sequencingSystem-level design considerations Mode Power-supply design considerations Power-supply decouplingDvdd DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speed Emif Data Lines Pins Where Data Present Emif big endian mode correctnessED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset Bootmode MIN NOM MAX Unit Recommended operating conditions‡IOH IOZ Parameter Test Conditions MIN TYP MAX Unit Parameter Measurement Information Signal transition levelsTester Pin Electronics Output Under Test = 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specifications Timing parameters and board routing analysis Board-Level Timings Example see Figure Control Signals † Output from DSPOutput from DSP Input and Output Clocks PLL Mode Bypass Mode UnitTiming requirements for Clkin †‡§ See Figure Parameter GDPA-167Clkin CLKOUT3 GDPA-167 ZDPA−167 Timing requirements for ECLKIN† see Figure−200 −250 Timing requirements for asynchronous memory cycles†‡§ Asynchronous Memory TimingSee −Figure Are CEx BE30 EA212 Address ED310 Read Data Setup = Strobe = Not ReadyAOE/SDRAS/SSOE † AWE/SDWE/SSWE † Ardy CEx BE30 EA212 Setup = Strobe = Not Ready Hold =AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory Timing BE1 BE2 BE3 BE4 CEx BE30EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing EA2113 Bank EA112 Column EA12 ED310 Read EclkoutAOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA2113 Write EclkoutEA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Actv EclkoutAOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310 Deac EclkoutRefr Eclkout CEx BE30 EA212 EA12 ED310 CEx BE30 EA212 MRS value ED310 MRS Eclkout Timing requirements for See Figure HOLD/HOLDA cycles† HOLD/HOLDA TimingHold Holda Eclkout Busreq Busreq Timing Timing requirements for reset†‡ see Figure Reset TimingCLKMODE0 = Clkin Eclkin Reset PhaseEmif Z Group† Emif Low Group† Group 2† Boot and Device Timing requirements for external interrupts† see Figure External Interrupt TimingEXTINT, NMI GDPA−167 HOST-PORT Interface TimingHstrobe Hstrobe Hrdy HCS Hrdy HR/W Hhwil Hstrobe † HCS HasHas † HR/W Hhwil Hstrobe ‡ HCS Hrdy HD150 input 1st halfword 2nd halfwordHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing FSR int Clks ClkrBitn-1 Clkx Clks Timing requirements for FSR when Gsync = 1 see FigureFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAX Clkx FSX MASTER§ Slave MINBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timing requirements for timer inputs† Timer TimingTINPx TOUTx Timing requirements for Gpio inputs†‡ GENERAL-PURPOSE INPUT/OUTPUT Gpio Port TimingGPIx GPOx Jtag TEST-PORT Timing DTCKL-TDOV Delay time, TCK low to TDO validTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for GDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for ZDP Mechanical Data Packaging Information Orderable Device Status Package Pins Package Eco PlanMSL Peak Temp Qty Seating Plane 4204396/A 04/02 GDP S-PBGA-N272 Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272 Important Notice