SPRS292 − OCTOBER 2005

HOST-PORT INTERFACE TIMING

timing requirements for host-port interface cycles†‡ (see Figure 42, Figure 43, Figure 44, and Figure 45)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

GDPA−167

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ZDPA−167

 

NO.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−200

 

UNIT

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

−250

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

MIN

MAX

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

1

tsu(SELV-HSTBL)

 

Setup time, select signals§ valid before

 

 

 

 

 

 

 

low

5

 

ns

HSTROBE

 

2

th(HSTBL-SELV)

 

Hold time, select signals§ valid after

 

 

 

 

 

 

 

 

 

low

4

 

ns

HSTROBE

 

3

tw(HSTBL)

 

Pulse duration,

HSTROBE

low (host read access)

4P

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Pulse duration, HSTROBE low (host write access)

4P

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

4

tw(HSTBH)

 

Pulse duration,

HSTROBE

high between consecutive accesses

4P

 

ns

10

tsu(SELV-HASL)

 

Setup time, select signals§ valid before

 

 

 

 

low

5

 

ns

HAS

 

11

t

 

Hold time, select signals§ valid after

 

 

 

 

 

low

3

 

ns

HAS

 

 

h(HASL-SELV)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

12

tsu(HDV-HSTBH)

 

Setup time, host data valid before

 

 

 

 

 

 

 

 

 

 

high

5

 

ns

 

HSTROBE

 

13

th(HSTBH-HDV)

 

Hold time, host data valid after

 

 

 

 

 

 

 

 

 

high

3

 

ns

 

HSTROBE

 

 

 

 

Hold time,

 

 

 

 

 

 

low after

 

 

 

 

 

low.

 

 

 

 

 

 

should not be inactivated until

 

 

 

14

th(HRDYL-HSTBL)

 

HSTROBE

HRDY

HSTROBE

2

 

ns

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

HRDY is active (low); otherwise, HPI writes will not complete properly.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

18

tsu(HASL-HSTBL)

 

Setup time,

 

 

 

low before

 

 

 

 

 

 

 

low

2

 

ns

 

HAS

HSTROBE

 

19

th(HSTBL-HASL)

 

Hold time,

 

 

low after

 

 

 

 

 

 

low

2

 

ns

 

HAS

HSTROBE

 

HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. § Select signals include: HCNTL[1:0], HR/W, and HHWIL.

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Motorola TMS320C6711D warranty HOST-PORT Interface Timing, GDPA−167, Hstrobe Hrdy, Has Hstrobe