HOST-PORT Interface Timing, GDPA−167 | Motorola TMS320C6711D

SPRS292 − OCTOBER 2005

HOST-PORT INTERFACE TIMING

timing requirements for host-port interface cycles†‡ (see Figure 42, Figure 43, Figure 44, and Figure 45)

GDPA−167

ZDPA−167

NO.

−200

UNIT

−250

MIN

MAX

1

tsu(SELV-HSTBL)

Setup time, select signals§ valid before

low

5

ns

HSTROBE

2

th(HSTBL-SELV)

Hold time, select signals§ valid after

low

4

ns

HSTROBE

3

tw(HSTBL)

Pulse duration,

HSTROBE

low (host read access)

4P

ns

Pulse duration, HSTROBE low (host write access)

4P

ns

4

tw(HSTBH)

Pulse duration,

HSTROBE

high between consecutive accesses

4P

ns

10

tsu(SELV-HASL)

Setup time, select signals§ valid before

low

5

ns

HAS

11

t

Hold time, select signals§ valid after

low

3

ns

HAS

h(HASL-SELV)

12

tsu(HDV-HSTBH)

Setup time, host data valid before

high

5

ns

HSTROBE

13

th(HSTBH-HDV)

Hold time, host data valid after

high

3

ns

HSTROBE

Hold time,

low after

low.

should not be inactivated until

14

th(HRDYL-HSTBL)

HSTROBE

HRDY

HSTROBE

2

ns

HRDY is active (low); otherwise, HPI writes will not complete properly.

18

tsu(HASL-HSTBL)

Setup time,

low before

low

2

ns

HAS

HSTROBE

19

th(HSTBL-HASL)

Hold time,

low after

low

2

ns

HAS

HSTROBE

†HSTROBE refers to the following logical operation on HCS, HDS1, and HDS2: [NOT(HDS1 XOR HDS2)] OR HCS.

‡P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns. § Select signals include: HCNTL[1:0], HR/W, and HHWIL.

POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

87

Image 87

Motorola TMS320C6711D warranty HOST-PORT Interface Timing, GDPA−167, Hstrobe Hrdy, Has Hstrobe

Contents

SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description C6711D Device characteristicsCharacteristics of the C6711D Processor Hardware Features Internal Clock Device compatibility Digital Signal Processor Functional block and CPU DSP core diagram CPU DSP core description ST2 ST1DA1 DA2 Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range HEX Address Range Acronym Register Name Peripheral register descriptionsEmif Registers L2 Cache Registers HEX Address Range Acronym Register Name Comments Interrupt Selector RegistersDevice Registers Edma Parameter RAM† Quick DMA Qdma and Pseudo Registers† Edma Registers PLL Controller Registers Gpio RegistersHPI Registers McBSP0 McBSP1 Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 and McBSP1 Registers Signal groups description CE0 CE3CE2 CE1 General-Purpose Input/Output Gpio Port GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 CLKOUT2/GP2 Device configurations at device reset Device Configurations Configuration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP IPD Description Name GDP IPU‡ ZDP Jtag Emulation Resets and Interrupts HD12 IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control Little Endian Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ Multichannel Buffered Serial Port 1 McBSP1 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ GENERAL-PURPOSE INPUT/OUTPUT Gpio Module Multichannel Buffered Serial Port 0 McBSP0 RSV RSV IPURSV IPD Supply voltage See Note Name GDP ZDP Supply Voltage PinsDvdd Cvdd GND Description Name GDP ZDP Supply Voltage PinsGround Pins VSS VSS PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS GND Description Name GDP ZDP Ground Pins Development support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Technology Device Family Temperature Range Default 0 C to 90 CPrefix Device Speed Range Documentation support PCC DCC Pgie GIE CPU CSR register descriptionRevision ID Pwrd CPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE Event DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector DSP Interrupts Interrupt Selector Edma module and Edma selector Edma ChannelsEdma Selector ESEL3 Register 0x01A0 FF0C ESEL1 Register 0x01A0 FF04 PLL and PLL controller MIN TYP MAX Unit PLL Lock and Reset TimesClkout Signals, Default Settings, and Control Enabled or Disabled Clock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 PLL Control/Status Register Pllcsr Pllcsr Register 0x01B7 C100 PLL Multiplier Control Register Pllm Pllm Register 0x01B7 C110 DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic PD3 PD2 PD1 Pwrd Field of the CSR Register Mode Power-supply sequencingCharacteristics of the Power-Down Modes System-level design considerations DSP Cvdd VSS GND Power-supply decouplingPower-supply design considerations Dvdd Ieee 1149.1 Jtag compatibility statement Example Boards and Maximum Emif Speed Emif device speed Emif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Reset Bootmode Recommended operating conditions‡ MIN NOM MAX UnitIOH IOZ Parameter Test Conditions MIN TYP MAX Unit Output Under Test Signal transition levelsParameter Measurement Information Tester Pin Electronics = 0.3 tcmax† VIL max VUS max Ground AC transient rise/fall time specifications Timing parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP See Figure PLL Mode Bypass Mode UnitInput and Output Clocks Timing requirements for Clkin †‡§ GDPA-167 ParameterClkin CLKOUT3 −250 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −200 Are Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ See −Figure AWE/SDWE/SSWE † Ardy Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AOE/SDRAS/SSOE † Setup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy Timing requirements for synchronous-burst Sram cycles† SYNCHRONOUS-BURST Memory Timing ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† CEx BE30BE1 BE2 BE3 BE4 EA212 ED310 Timing requirements for synchronous Dram cycles† see Figure Synchronous Dram Timing Read Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Write EclkoutEA2113 EA12 ED310 Dcab Eclkout Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† CEx BE30 EA212 EA12 ED310 Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 Refr Eclkout CEx BE30 EA212 MRS value ED310 MRS Eclkout HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Eclkout Busreq Busreq Timing Reset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Hstrobe Hrdy HOST-PORT Interface TimingGDPA−167 Hstrobe HCS Hrdy HR/W Hhwil Hstrobe ‡ HCS HasHR/W Hhwil Hstrobe † HCS Has † HD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clkx Clks ClkrFSR int Bitn-1 Master Slave MIN MAX Timing requirements for FSR when Gsync = 1 see FigureClks FSR external CLKR/X no need to resync CLKR/X needs resync MASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx TCK TDO TDI/TMS/TRST DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing Timing requirements for Jtag test port see Figure Mechanical Data Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Thermal resistance characteristics S-PBGA package for ZDP Qty Orderable Device Status Package Pins Package Eco PlanPackaging Information MSL Peak Temp Seating Plane 4204396/A 04/02 GDP S-PBGA-N272 Seating Plane 4204398/A 04/02 ZDP S-PBGA-N272 Important Notice