Jtag TEST-PORT Timing, Tck Tdo Tdi/Tms/Trst

SPRS292 − OCTOBER 2005

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 54)

					GDPA−167
					ZDPA−167
NO.					−200		UNIT
					−250
					MIN	MAX

1	tc(TCK)	Cycle time, TCK			35		ns
3	tsu(TDIV-TCKH)
3	tsu(TDIV-TCKH)	Setup time, TDI/TMS/TRST		valid before TCK high	10		ns
4	th(TCKH-TDIV)		valid after TCK high		7		ns
4	th(TCKH-TDIV)	Hold time, TDI/TMS/TRST	valid after TCK high		7		ns

switching characteristics over recommended operating conditions for JTAG test port (see Figure 54)

		GDPA−167
		ZDPA−167
NO.	PARAMETER	−200		UNIT
		−250
		MIN	MAX
2	td(TCKL-TDOV)Delay time, TCK low to TDO valid	0	15	ns
	1
	TCK
	2	2
	TDO
		4
		3

TDI/TMS/TRST

Figure 54. JTAG Test-Port Timing

102	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Page 102

Image 102

Motorola TMS320C6711D Jtag TEST-PORT Timing, Timing requirements for Jtag test port see Figure, Tck Tdo Tdi/Tms/Trst

Contents

SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Hardware Features Internal Clock Device characteristicsCharacteristics of the C6711D Processor C6711D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description DA2 ST1DA1 ST2 Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range L2 Cache Registers Peripheral register descriptionsEmif Registers HEX Address Range Acronym Register Name Edma Parameter RAM† Interrupt Selector RegistersDevice Registers HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† PLL Controller Registers Gpio RegistersHPI Registers McBSP0 and McBSP1 Registers Timer 0 and Timer 1 RegistersHEX Address Range Acronym Register Name Comments Timer McBSP0 McBSP1 Signal groups description CE1 CE3CE2 CE0 CLKOUT2/GP2 GpioGP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4 General-Purpose Input/Output Gpio Port Device Configurations Device configurations at device reset Configuration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag Emulation Little Endian IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPIUsed for transfer of data, address, and control HD12 Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV RSV IPURSV IPD Cvdd Name GDP ZDP Supply Voltage PinsDvdd Supply voltage See Note VSS Description Name GDP ZDP Supply Voltage PinsGround Pins GND PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS Description Name GDP ZDP Ground Pins VSS GND Development support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Device Speed Range Device Family Temperature Range Default 0 C to 90 CPrefix Technology Documentation support Pwrd CPU CSR register descriptionRevision ID PCC DCC Pgie GIE CPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupts Interrupt Selector DSP Interrupt Default Selector Module ControlInterrupt sources and interrupt selector Event Edma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller Enabled or Disabled PLL Lock and Reset TimesClkout Signals, Default Settings, and Control MIN TYP MAX Unit Clock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 System-level design considerations Power-supply sequencingCharacteristics of the Power-Down Modes Mode Dvdd Power-supply decouplingPower-supply design considerations DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed Emif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode Reset Recommended operating conditions‡ MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZ Tester Pin Electronics Signal transition levelsParameter Measurement Information Output Under Test AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP Timing requirements for Clkin †‡§ PLL Mode Bypass Mode UnitInput and Output Clocks See Figure GDPA-167 ParameterClkin CLKOUT3 −200 Timing requirements for ECLKIN† see FigureGDPA-167 ZDPA−167 −250 See −Figure Asynchronous Memory TimingTiming requirements for asynchronous memory cycles†‡§ Are AOE/SDRAS/SSOE † Setup = Strobe = Not ReadyCEx BE30 EA212 Address ED310 Read Data AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles† EA212 ED310 CEx BE30BE1 BE2 BE3 BE4 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure Read Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† EA12 ED310 Write EclkoutEA2113 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Actv EclkoutCEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310 Dcab Eclkout Refr Eclkout Deac EclkoutCEx BE30 EA2113 Bank EA112 EA12 ED310 CEx BE30 EA212 EA12 ED310 MRS Eclkout CEx BE30 EA212 MRS value ED310 HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Busreq Timing Eclkout Busreq Reset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI Hstrobe HOST-PORT Interface TimingGDPA−167 Hstrobe Hrdy HCS Hrdy Has † HasHR/W Hhwil Hstrobe † HCS HR/W Hhwil Hstrobe ‡ HCS HD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Bitn-1 Clks ClkrFSR int Clkx FSR external CLKR/X no need to resync CLKR/X needs resync Timing requirements for FSR when Gsync = 1 see FigureClks Master Slave MIN MAX MASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx Timing requirements for Jtag test port see Figure DTCKL-TDOV Delay time, TCK low to TDO validJtag TEST-PORT Timing TCK TDO TDI/TMS/TRST Thermal resistance characteristics S-PBGA package for ZDP Package thermal resistance characteristicsThermal resistance characteristics S-PBGA package for GDP Mechanical Data MSL Peak Temp Orderable Device Status Package Pins Package Eco PlanPackaging Information Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice

JTAG TEST-PORT TIMING

timing requirements for JTAG test port (see Figure 54)

GDPA−167

MIN

PARAMETER

td(TCKL-TDOV)Delay time, TCK low to TDO valid

TCK

TDO

TDI/TMS/TRST

Figure 54. JTAG Test-Port Timing