Terminal Functions, PIN Signal | Motorola TMS320C6711D guide

SPRS292A − OCTOBER 2005 − REVISED NOVEMBER 2005

								Terminal Functions
			PIN
	SIGNAL		NO.	TYPE†	IPD/			DESCRIPTION
	SIGNAL				IPD/
	NAME		GDP/		IPU‡
	NAME		GDP/		IPU‡
			ZDP

								CLOCK/PLL

	CLKIN		A3	I	IPD	Clock Input

						For this device, the CLKOUT2 pin is multiplexed with the GP[2] pin.
						Clock output at half of device speed (O/Z) [default] (SYSCLK2 internal signal from the clock
						generator) or this pin can be programmed as GP[2] (I/O/Z).
	CLKOUT2		Y12	O/Z	IPD
	(/GP0[2])		Y12	O/Z	IPD	When the CLKOUT2 pin is enabled, the CLK2EN bit in the EMIF global control register
	(/GP0[2])
						(GBLCTL) controls the CLKOUT2 pin (All devices).
						CLK2EN = 0: CLKOUT2 is disabled
						CLK2EN = 1: CLKOUT2 enabled to clock [default]

	CLKOUT3		D10	O	IPD	Clock output programmable by OSCDIV1 register in the PLL controller.

						Clock generator input clock source select
						0	−	Reserved. Do not use.
	CLKMODE0		C4	I	IPU	1	−	CLKIN square wave [default]
						For proper device operation, this pin must be either left unconnected or externally pulled up with
						a 1-kΩresistor.

	PLLHV		C5	A		Analog power (3.3 V) for PLL

								JTAG EMULATION

	TMS		B7	I	IPU	JTAG test-port mode select

	TDO		A8	O/Z	IPU	JTAG test-port data out

	TDI		A7	I	IPU	JTAG test-port data in

	TCK		A6	I	IPU	JTAG test-port clock

						JTAG test-port reset. For IEEE 1149.1 JTAG compatibility, see the IEEE 1149.1
	TRST§		B6	I	IPD
	TRST§		B6	I	IPD	JTAG Compatibility Statement section of this data sheet.
						JTAG Compatibility Statement section of this data sheet.

	EMU5		B12	I/O/Z	IPU	Emulation pin 5. Reserved for future use, leave unconnected.

	EMU4		C11	I/O/Z	IPU	Emulation pin 4. Reserved for future use, leave unconnected.

	EMU3		B10	I/O/Z	IPU	Emulation pin 3. Reserved for future use, leave unconnected.

†I = Input, O = Output, Z = High impedance, S = Supply voltage, GND = Ground, A = Analog signal (PLL Filter)

‡IPD = Internal pulldown, IPU = Internal pullup. [To oppose the supply rail on these IPD/IPU signal pins, use external pullup or pulldown resistors no greater than 4.4 kΩ and 2.0 kΩ, respectively.]

§To ensure a proper logic level during reset when these pins are both routed out and 3−stated or not driven, it is recommended an external 10-k Ω pullup/pulldown resistor be included to sustain the IPU/IPD, respectively.

24	POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443

Image 24

Motorola TMS320C6711D warranty Terminal Functions, PIN Signal, IPD Description Name GDP IPU‡ ZDP

Contents

SPRS292A − October 2005 − Revised November Table of Contents Revision History Pages ADDITIONS/CHANGES/DELETIONSMultichannel Buffered Serial Port Timing GDP and ZDP BGA packages bottom view GDP and ZDP 272-PIN Ball Grid Array BGA PACKAGES†Bottom View Description Device characteristics Characteristics of the C6711D ProcessorHardware Features Internal Clock C6711D Device compatibility Functional block and CPU DSP core diagram Digital Signal Processor CPU DSP core description ST1 DA1DA2 ST2 Memory map summary TMS320C6711D Memory Map SummaryMemory Block Description Block Size Bytes HEX Address Range Peripheral register descriptions Emif RegistersL2 Cache Registers HEX Address Range Acronym Register Name Interrupt Selector Registers Device RegistersEdma Parameter RAM† HEX Address Range Acronym Register Name Comments Edma Registers Quick DMA Qdma and Pseudo Registers† PLL Controller Registers Gpio RegistersHPI Registers Timer 0 and Timer 1 Registers HEX Address Range Acronym Register Name Comments TimerMcBSP0 and McBSP1 Registers McBSP0 McBSP1 Signal groups description CE3 CE2CE1 CE0 Gpio GP7EXTINT7 GP6EXTINT6 GP5EXTINT5 GP4EXTINT4CLKOUT2/GP2 General-Purpose Input/Output Gpio Port Device Configurations Device configurations at device reset Configuration GDP/ZDP Functional Description PIN BOOTMODE‡CLKMODE0 Devcfg register description EksrcBIT # Name Description Terminal Functions PIN Signal Terminal FunctionsIPD Description Name GDP IPU‡ ZDP Resets and Interrupts IPD Description Name GDP IPU‡ ZDP Jtag Emulation IPD Description Name GDP IPU‡ ZDP HOST-PORT Interface HPI Used for transfer of data, address, and controlLittle Endian HD12 Only one asserted during any external data access Decoded from the two lowest bits of the internal addressEmif − ASYNCHRONOUS/SYNCHRONOUS Memory Control ¶ IPD Description Name GDP IPU‡ ZDP Emif − Address ¶ EA9 EA8 EA7 EA6 EA5 EA4 EA3 EA2 IPD Description Name GDP IPU‡ ZDP Emif − Data ¶ Multichannel Buffered Serial Port 1 McBSP1 Multichannel Buffered Serial Port 0 McBSP0 GENERAL-PURPOSE INPUT/OUTPUT Gpio Module RSV RSV IPURSV IPD Name GDP ZDP Supply Voltage Pins DvddCvdd Supply voltage See Note Description Name GDP ZDP Supply Voltage Pins Ground PinsVSS GND PIN Signal TYPE† Description Name GDP ZDP Ground Pins VSS Description Name GDP ZDP Ground Pins VSS GND Development support Software Development ToolsHardware Development Tools Device support Device and development-support tool nomenclatureFully qualified production device Device Family Temperature Range Default 0 C to 90 C PrefixDevice Speed Range Technology Documentation support CPU CSR register description Revision IDPwrd PCC DCC Pgie GIE CPU CSR Register Bit Field Description CPU IDPCC Cache configuration Ccfg register description Ccfg Register Bit Field DescriptionL2MODE DSP Interrupt Default Selector Module Control Interrupt sources and interrupt selectorDSP Interrupts Interrupt Selector Event Edma module and Edma selector Edma ChannelsEdma Selector ESEL1 Register 0x01A0 FF04 ESEL3 Register 0x01A0 FF0C PLL and PLL controller PLL Lock and Reset Times Clkout Signals, Default Settings, and ControlEnabled or Disabled MIN TYP MAX Unit Clock Signal PLL Clock Frequency Ranges†‡GDPA−167, ZDPA-167 Pllcsr Register 0x01B7 C100 PLL Control/Status Register Pllcsr Pllm Register 0x01B7 C110 PLL Multiplier Control Register Pllm DxEN OSCDIV1 Register 0x01B7 C124 Oscillator Divider 1 Register OSCDIV1OD1EN General-purpose input/output Gpio GP7 GP6 GP5 GP4 GP2DIR Power-down mode logic Pwrd Field of the CSR Register PD3 PD2 PD1 Power-supply sequencing Characteristics of the Power-Down ModesSystem-level design considerations Mode Power-supply decoupling Power-supply design considerationsDvdd DSP Cvdd VSS GND Ieee 1149.1 Jtag compatibility statement Emif device speed Example Boards and Maximum Emif Speed Emif big endian mode correctness Emif Data Lines Pins Where Data PresentED3124 BE3 ED2316 BE2 ED158 BE1 ED70 BE0 Bootmode Reset Recommended operating conditions‡ MIN NOM MAX UnitIOH Parameter Test Conditions MIN TYP MAX Unit IOZ Signal transition levels Parameter Measurement InformationTester Pin Electronics Output Under Test AC transient rise/fall time specifications = 0.3 tcmax† VIL max VUS max Ground Timing parameters and board routing analysis Control Signals † Output from DSP Board-Level Timings Example see FigureOutput from DSP PLL Mode Bypass Mode Unit Input and Output ClocksTiming requirements for Clkin †‡§ See Figure GDPA-167 ParameterClkin CLKOUT3 Timing requirements for ECLKIN† see Figure GDPA-167 ZDPA−167−200 −250 Asynchronous Memory Timing Timing requirements for asynchronous memory cycles†‡§See −Figure Are Setup = Strobe = Not Ready CEx BE30 EA212 Address ED310 Read DataAOE/SDRAS/SSOE † AWE/SDWE/SSWE † Ardy Setup = Strobe = Not Ready Hold = CEx BE30 EA212AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Ardy SYNCHRONOUS-BURST Memory Timing Timing requirements for synchronous-burst Sram cycles† CEx BE30 BE1 BE2 BE3 BE4EA212 ED310 ARE/SDCAS/SSADS† AOE/SDRAS/SSOE† AWE/SDWE/SSWE† Synchronous Dram Timing Timing requirements for synchronous Dram cycles† see Figure Read Eclkout EA2113 Bank EA112 Column EA12 ED310AOE/SDRAS/SSOE † ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Write Eclkout EA2113EA12 ED310 AOE/SDRAS/SSOE † ARE/SDCAS/SSADS † AWE/SDWE/SSWE † Actv Eclkout CEx BE30 EA2113 Bank Activate EA112 Row Address EA12 ED310AOE/SDRAS/SSOE† ARE/SDCAS/SSADS† AWE/SDWE/SSWE† Dcab Eclkout Deac Eclkout CEx BE30 EA2113 Bank EA112 EA12 ED310Refr Eclkout CEx BE30 EA212 EA12 ED310 MRS Eclkout CEx BE30 EA212 MRS value ED310 HOLD/HOLDA Timing Timing requirements for See Figure HOLD/HOLDA cycles†Hold Holda Busreq Timing Eclkout Busreq Reset Timing Timing requirements for reset†‡ see FigureCLKMODE0 = Phase Clkin Eclkin ResetEmif Z Group† Emif Low Group† Group 2† Boot and Device External Interrupt Timing Timing requirements for external interrupts† see FigureEXTINT, NMI HOST-PORT Interface Timing GDPA−167Hstrobe Hstrobe Hrdy HCS Hrdy Has HR/W Hhwil Hstrobe † HCSHas † HR/W Hhwil Hstrobe ‡ HCS HD150 input 1st halfword 2nd halfword HrdyHD150 input 1st half-word 2nd half-word −1 ¶ Multichannel Buffered Serial Port Timing Clks Clkr FSR intBitn-1 Clkx Timing requirements for FSR when Gsync = 1 see Figure ClksFSR external CLKR/X no need to resync CLKR/X needs resync Master Slave MIN MAX MASTER§ Slave MIN Clkx FSXBit Bitn-1 MASTER§ Slave MIN MAX GDPA-167 McBSP Timing as SPI Master or Slave Clkstp = 10b, Clkxp = McBSP Timing as SPI Master or Slave Clkstp = 11b, Clkxp = Timer Timing Timing requirements for timer inputs†TINPx TOUTx GENERAL-PURPOSE INPUT/OUTPUT Gpio Port Timing Timing requirements for Gpio inputs†‡GPIx GPOx DTCKL-TDOV Delay time, TCK low to TDO valid Jtag TEST-PORT TimingTiming requirements for Jtag test port see Figure TCK TDO TDI/TMS/TRST Package thermal resistance characteristics Thermal resistance characteristics S-PBGA package for GDPThermal resistance characteristics S-PBGA package for ZDP Mechanical Data Orderable Device Status Package Pins Package Eco Plan Packaging InformationMSL Peak Temp Qty GDP S-PBGA-N272 Seating Plane 4204396/A 04/02 ZDP S-PBGA-N272 Seating Plane 4204398/A 04/02 Important Notice