Motorola TMS320C6711D warranty Timing requirements for FSR when Gsync = 1 see Figure, Clks

SPRS292 − OCTOBER 2005

MULTICHANNEL BUFFERED SERIAL PORT TIMING (CONTINUED)

timing requirements for FSR when GSYNC = 1 (see Figure 47)

					GDPA−167
					ZDPA−167
NO.					−200		UNIT
					−250
					MIN	MAX
1	tsu(FRH-CKSH)	Setup time, FSR high before CLKS high			4		ns
2	th(CKSH-FRH)	Hold time, FSR high after CLKS high			4		ns
		CLKS
			1	2

FSR external

CLKR/X (no need to resync)

CLKR/X (needs resync)

Figure 47. FSR Timing When GSYNC = 1

timing requirements for McBSP as SPI master or slave: CLKSTP = 10b, CLKXP = 0†‡ (see Figure 48)

			GDPA−167
			ZDPA−167
NO.				−200			UNIT
				−250
			MASTER		SLAVE
			MIN MAX		MIN	MAX
4	tsu(DRV-CKXL)	Setup time, DR valid before CLKX low	12		2 − 6P		ns
5	th(CKXL-DRV)	Hold time, DR valid after CLKX low	4		5 + 12P		ns

†P = 1/CPU clock frequency in ns. For example, when running parts at 250 MHz, use P = 4 ns.

‡For all SPI slave modes, CLKG is programmed as 1/2 of the CPU clock by setting CLKSM = CLKGDV = 1.

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