Paradyne 317x E1 Table C-2 2 of Port Configuration Options, Rcv RAI Halt Next None Halt Prev

ACCULINK 317x E1 DSU/CSU

Table C-2

(2 of 4)

Port Configuration Options

All Ones: Both

Next Disab DTR RTS Both Prev

Send All Ones on Data Port Not Ready. Specifies the conditions on the data port that determine when valid data is not being sent from the DTE. When this condition is detected, all ones are sent to the network on the DS0 channels allocated to the port.

Disab ± Disables the monitoring of interchange circuits from the DTE connected to this port.

DTR ± Monitors the DTE Ready interchange circuit CD (CCITT 108/1/2). When DTR is interrupted, all ones are sent to the network.

RTS ± Monitors the Request-to-Send interchange circuit CA (CCITT 105). When RTS is interrupted, all ones are sent to the network.

Both ± Monitors both DTR and RTS. If either is interrupted, all ones are sent to the network.

NOTE: For X.21 applications, set this configuration option to RTS or Disab.

Rcv RAI: Halt

Next None Halt Prev

Action on Network RAI Alarm. Specifies the action taken on this port when a Remote Alarm Indication (RAI) is received on the network interface.

None ± Makes the data port unaffected by RAIs received on the network interface.

Halt ± Stops the transmission of data on the port and disables the data port when RAIs are received on the network interface. When RAIs are received, all ones are sent on the Received Data interchange circuit BB (CCITT 104). The Clear-to-Send interchange circuit CB (CCITT 106) is interrupted.

Tx Clock: Int

Next Int Ext Prev

Data Port Transmit Clock. Specifies whether the transmitted data for the port is clocked using an internal clock provided by the E1 DSU/CSU (synchronized to the clock source specified by the clock source configuration options in the General configuration option group) or an external clock provided by the DTE connected to the port. When an external clock is used, it must be synchronized to the same clock source as the E1 DSU/CSU.

Int ± Indicates the clock is provided internally by the E1 DSU/CSU on the TXC interchange circuit DB (CCITT 114).

Ext ± Indicates the clock is provided externally by the DTE on the XTXC interchange circuit DA (CCITT 113). Use this selection when either the primary or secondary clock source is set to this data port.

InvertTxC: Disab

Next Enab Disab Prev

Invert Transmit Clock. Specifies whether the clock supplied by the E1 DSU/CSU on the TXC interchange circuit DB (CCITT 114) is phase inverted with respect to the Transmitted Data interchange circuit BA (CCITT 103). This configuration option is useful when long cable lengths between the E1 DSU/CSU and the DTE are causing data errors.

Enab ± Indicates TXC supplied by the E1 DSU/CSU on this port is phase inverted.

Disab ± Indicates TXC supplied by the E1 DSU/CSU on this port is not phase inverted.

InvrtData: Disab

Next Enab Disab Prev

Invert Transmitted and Received Data. Specifies whether the port's transmitted data and received data are logically inverted before being transmitted or received. This configuration option is useful for applications where HDLC data is being transported. Inverting the data ensures that the density requirements for the network Interface are met.

Enab ± Indicates the transmitted data and received data for this port are inverted.

Disab ± Indicates the transmitted data and received data for this port are not inverted.

C-4 December 1996 3170-A2-GB20-20