PIN Configuration, Network Interface | SMC Networks SMC91C95

Network Interface	∙ Four Direct Driven LEDs for Status/
	Diagnostics

∙Integrates 10BASE-T Transceiver

Functions:		Software Drivers
-	Driver and Receiver
-	Link Integrity Test	∙ Uses Certified SMC9000 Drivers Which
- Receive Polarity Detection and		Operate with Every Major Network
	Correction	Operating System
∙ Integrates AUI Interface		∙ Software Driver Compatible with
∙ Implements 10 Mbps Manchester		SMC91C92, SMC91C94 and SMC91C100
Encoding/Decoding and Clock Recovery		(100 Mbps) Controllers in ISA Mode
∙ Automatic Retransmission, Bad Packet		∙ Software Driver Utilizes Full Capability of
Rejection, and Transmit Padding		32 Bit Microprocessor
∙ External and Internal Loopback Modes

PIN CONFIGURATION

AVDD

TXP/nCOLL

TXN/nCRS

TPETXP

TEPTXDP

TPETXN

TPETXDN AVSS nTXLED/nTXEN nRXLED/RXCLK nLINKLED/TXD nBSELED/RXD

VDD SPKRIN SPKROUT nMIS16

MRDY

MINT

VSS MRINGIN nMRINGOA

MRINGOB nMCS nMRESET

VDD MIDLEN1 nMPWDN nMPDOUT MFBK1

VSS

NC

ND

	NC		AVSS		COLN		COLP		RECN		RECP		TPERXN		TPERXP		AVDD		AVSS		RBIAS		AVDD		nXENDEC		nEN16		PWRDWN/TXCLK		nROM/nPCMCIA		VSS		ENEEP		EESK		EECS		EEDO/SDOUT		EEDI		IOS2		IOS1		VDD		IOS0		XTAL2		XTAL1		WAKEUP		nWAKEUP EN		RESET		NC



1	128		127		126		125		124		123	122		121			120		119	118		117			116		115	114		113			112		111		110	109			108		107	106			105		104		103		102	101			100		99		98	97
1																																																														96
2																																																														95
3																																																														94
4																																																														93
5																																																														92
6																																																														91
7																																																														90
8																																																														89
9																																																														88
10																																																														87
11																																																														86
12											SMC91C95																																																			85
13																																																														84
16																																																														81
14																																																														83
15																																																														82
17				128 Pin VTQFP																																																										80
18																																																														79
21																																																														76
19																																																														78
20																																																														77
22																																																														75
23																																																														74
24																																																														73
25																																																														72
26																																																														71
27																																																														70
28																																																														69
29																																																														68
30																																																														67
31																																																														66
32																																																														65
	33		34		35		36		37		38	39		40			41		42	43		44			45		46	47		48			49		50		51	52			53		54	55			56		57		58		59	60			61		62		63	64

NC

NC

VSS

INTR3

INTR2/nSTSCHG

INTR1/nINPACK

INTR0/nIREQ

VDD nIORD nIOWR nMEMR/nOE nIOSC16/nIOIS16

VSS IOCHRDY/nWAIT BALE/nWE nSBHE/nCE2

VDD

D15

D14

D13

D12

VSS

D11

D10

D9

VDD

D8

D7

D6

VSS

D5

D4

NC

AEN/nREG

A0

A1

VDD

A2

A3

A4

A5

A6

A7

VSS

A8

A9

A10

A11

A12

A13

VDD

A14

A15

A16/nFWE

A17/nFCS

A18

A19/nCE1

VSS

D0

D1

D2

VDD

D3

NC

3

Image 3

SMC Networks SMC91C95 manual PIN Configuration, Network Interface, Software Drivers

Contents

Bus Interface Features Table of Contents PIN Configuration Network InterfaceSoftware Drivers Overview General DescriptionPage Uses non-volatile jumperless setup via serial Eeprom ISAPcmcia PIN Requirements Function ISA Pcmcia Number Pins Coln Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GNDTotal Pins Recp Description of PIN Functions PIN no Name Symbol Type Description Reset ISA Byte High Enable input. Asserted lowPcmcia Card Enable 2 input. Used to Enable Select card on odd byte accesses Ready Register. This interrupt is tri-stated when not Application of the VCC or Reset which everISA Output. Active high interrupt signal. Value of INT SEL1-0 bits in the Configuration Interrupt pin if enabled Whenever the SMC91C95 is in 16 bit modeEnable Function bit in the Ecor Is with Input. Active low read strobe used to access Pin when enabled by the Audio bit Modem Pin is active high when either the PwrdwnOutput B Powerdown mode Pwrdwn bit is zero Value of the Mringin input. When entering Sdout Eeprom Eeprom EeskEeprom Eecs Eeprom Eedo AUI RxclkTXD Register Tperxn TPE Tpetxp TPE TpetxdpTxclk Buffer Types EndecVSS Avss SMC91C95 SMC91C95 SMC91C95 Internal Block Diagram Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15 BIT ModeFunctional Description Even byte Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15Even byte IOis8=1 + nEN16=1.16BIT=0 No Cycle Signals ISA Pcmci ON-CHIP Depth Width Used SMC91C95 Address SpacesROM Buffer Memory Mapping and Paging VS. Receive and TX Area CPU Side TX Fifo TX CompletionFifo Receive Queue and Mapping With Block DiagramSMC91C95 Internal Transmit Packet Receive Packet Packet Format in Buffer Memory ODD CRC ODDByte before the Control Byte should be ignored Address Hash Value Multicast Table BIT Receive Frame Status Word SMC91C95 Interrupt Merging Function Pcmcia Mode ISA ModeInterrupt Output NIREQ when either function is Interrupt Structure Mcor Reset LogicReset Functions Ecor Pwrdwn Powerdown LogicPowerdown Functions Powerdown Powers Does not Entered Exited Power Down Pcmcia Attribute Memory Address 0- 7FFEh Pcmcia Configuration Registers Address 8000-803Eh 7FFEh 8000h 803Eh Attribute Memory Address Using Serial Eeprom Offsetname ISA and Pcmcia ModeTypesymbol Space BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 Internal I/O Space Mapping BS2 BS1 BS0 BANK# Bank Select Register Offset Name Type Symbol READ/WRITE BSRHigh Byte LOW BS2 BS0 LOW Pade Forco Loop Txena Byte High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet AUI Fdse Fduplx Ephloop Loop Loops AT Network Transmits LTX MUL High Link CTR EXC Lost Latcol Wakeu ByteOvrn Carr LOW LTX SqetPage Rxabort Rxovrnint High SoftStrip Rxen Byte RST CAR LOW Almul Prms Byte AbortPage FFH Memory Size Actual Memory Register Device Space BANK0 Offset Name Type Symbol Memory ConfigurationMCR Register READ/WRITE INT Byte High Full SET AUI Byte Wait StepSelec DIS INT SEL1 INT SEL0 Interrupt PIN Used RA15 RA14 A15 A14 A13Byte LOW ROM Size RA17 High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte Release LOW Eeprom Reload Store Byte Enable High RCVWakeu Auto Byte BAD Pcmcia Eeprom to Sram Memory Map 3FF 3FA3FC 3FD 000 0 Noop no Operation High Byte LOW Command N0/BUSCommand SET xyz Busy Bit Readable Command Sequencing Failed Allocated Packet Number This register is updated upon an Allocate Memory MMU commandPage Page Space BANK2 Offset Name Type Symbol Through AhData Register READ/WRITE Data High Data LOW Ercv INT Rxovr Empty TX INT Ercv EPH INT Rxovr Alloc TX INT RCV INT EmptyPage INT LOW Multicast Table Byte High Bit MDO NXNDEIOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO MDOE=0 MDOE=1 Chip ID Value Device High Byte LOW Byte Chip REV Byte Discr High Byte LOW RCV Theory of Operation Memory ArchitectureFull Duplex Ethernet Support Main 802.3 section affected by Fdse is Behavior in Fdse Mode Typical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine MMU RAM CSMA/CD RX Intr Assumes Auto Release Option Selected TX Intr Txempty Intr Driver Send and Allocate Routines Interrupt Generation Memory Partitioning Internal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Ireq Pcmcia Configuration Registers DescriptionSreset Wrattri IOIs8 8002h Ethernet Configuration and Status Register EcsrPage Pcmcia functionality, this bit must be set LevIREQ Enable IOIs8 Reserved Audio Current Value Value Written NEW Value 8024h Pin Replacement Register PRR 8028h Extended Status RegisterESR Ringevent Ringenable A15 A14 A13 A12 A11 A10 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register 8032h Modem I/O Size Register Functional Description of the Blocks Memory Management UnitArbiter Wait State Policy BUS Interface DMA Block Packet Number Fifos MMU Packet Number Flow and Relevant Registers DMA Csma Block Physical Interface Network Interface10BASE-T AUI Transmit Functions Receive Functions Page Register Address Board Setup Information ISA ModeEthernet Individual Address I/O Base Address Eeprom Word Arbitration Considerations Diagnostic LEDsPage 103 64 X 16 Serial Eeprom MAP for ISA Mode Maximum Guaranteed Ratings Operational DescriptionParameter Symbo MIN TYP MAX Units Comments Type Buffer Input LeakageIP Type Buffers ID Type Buffers Limits Parameter Symbo MIN TYP MAX Unit Test Condition OD16 Type BufferOD162 Type Buffer OD24 Type Buffer Parameter MIN TYP MAX Units Capacitive Load on OutputsINTRO-INTR3 108 Timing DiagramsA50, nREG NCE1 NOE D150 30 max Max Min Data Valid Address/nREG Setup Time to NWE Low NWE High NCE1 Low to nWE High Setup109 110 O Read Timing Table on the following Parameter Min Typ Max Units 112 O Write Timing Table on the following 100 114 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 115 NINPAC 116 Consecutive Pcmcia Write Cycles 117 Pcmcia Attribute Memory READ/WRITE A15=0 118 Mringoutb 119 ISA Consecutive Read Cycles 120 ISA Consecutive Write Cycles 121 ISA Consecutive Read and Write Cycles 122 Data Register Special Read Access 123 Data Register Special Write Access 124 BIT Mode Register Cycles 125 ISA Register Access When Using Bale 126 External ROM Read Access Using Bale 127 Eeprom Read 128 Eeprom Write 129 Memory Read Timing 130 External Endec Interface Start of Transmit 131 Differential Output Signal Timing 10BASE-T and AUI Tperxpn Recp Recn Tperxp Tperxn Recp Recn 134 Transmit Timing END of Frame AUI and 10BASE-T 135 Collision Timing AUI 136 Vtqfp Package OutlinePage Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516