REGISTER are written in the EEPROM locations defined by the
The three least significant bits of the CONTROL REGISTER (EEPROM SELECT, RELOAD and STORE) are used to control the EEPROM. Their values are not stored nor loaded from the
EEPROM.
b) GENERAL PURPOSE REGISTER - EEPROM SELECT bit = 1
On EEPROM read operations (after setting RELOAD high) the EEPROM word address defined by the POINTER REGISTER 6 least significant bits is read into the GENERAL PURPOSE REGISTER.
On EEPROM write operations (after setting the STORE bit) the value of the GENERAL PURPOSE REGISTER is written at the EEPROM word address defined by the POINTER REGISTER 6 least significant bits.
RELOAD and STORE are set by the user to initiate read and write operations respectively. Polling the value until read low is used to determine completion. When an EEPROM access is in progress the STORE and RELOAD bits of CTR will readback as both bits high. No other bits of the SMC91C95 can be read or written until the EEPROM operation completes and both bits are clear. This mechanism is also valid for reset initiated reloads.
NOTE: If no EEPROM is connected to the SMC91C95, for example for some embedded applications, the ENEEP pin should be grounded and no accesses to the EEPROM will be attempted. Configuration, Base, and Individual Address assume their default values upon hardware reset and the CPU is responsible for programming them for their final value.
DIAGNOSTIC LEDs
The following LED drive signals are available for diagnostic and installation aid purposes:
nTXLED - Activated by transmit activity.
nBSELED - Board select LED. Activated when the board space is accessed, namely on accesses to the SMC91C95 register space or the ROM area decoded by the SMC91C95. The signal is stretched to 125 msec.
nRXLED - Activated by receive activity.
nLINKLED - Reflects the link integrity status.
ARBITRATION CONSIDERATIONS
The arbiter exploits the sequential nature of the CPU accesses to provide a very fast access time. Memory bandwidth considerations will have an effect on the CPU cycle time but no effect on access time.
For normal 8 MHz, 10 MHz and 12.5 MHz ISA buses as well as EISA normal cycles the SMC91C95 can be accessed without negating ready.
When write operations occur, the data is written into a FIFO. The CPU cycle can complete immediately, and the buffered data will be
written into memory later. The memory arbitration request is generated as a function of that FIFO being not empty. The nature of the cycle requested (byte/word) is determined by the lsb of the pointer and the number of bytes in the FIFO.
When read operations occur, words are pre- fetched upon pointer loading in order to have at least a word ready in the FIFO to be read. New
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