SMC Networks SMC91C95 manual Buffer Memory

The internal DMA interface can arbitrate for RAM access and request memory from the MMU when necessary.

An encoder/decoder block interfaces the CSMA/CD block on the serial side. The encoder will do the Manchester encoding of the transmit data at 10 Mbps, while the decoder will recover the receive clock and decode received data.

Carrier and Collision detection signals are also handled by this block and relayed to the CSMA/CD block.

The encoder/decoder block can interface the network through the AUI interface pairs or it can be programmed to use the internal 10BASE-T transceiver and connect to a twisted pair network.

The twisted pair interface takes care of the medium dependent signaling for 10BASE-T type of networks. It is responsible for line interface (with external pulse transformers and pre-distortion resistors), collision detection as well as the link integrity test function.

The SMC91C95 provides a 16-bit data path into RAM. The RAM is private and can only be accessed by the system via the arbiter. RAM memory is managed by the MMU. Byte and word accesses to the RAM are supported.

If the system to SRAM bandwidth is insufficient, the SMC91C95 will automatically use its IOCHRDY line for flow control. However, for ISA buses, IOCHRDY will never be negated.

BUFFER MEMORY

The logical addresses for RAM access are divided into TX area and RX area. Each one of the areas is 1.536 kbytes long and accommodates one maximum size Ethernet packet.

24

The TX area is seen by the CPU as a window through which packets can be loaded into memory before queuing them in the TX FIFO of packets. The TX area can also be used to examine the transmit completion status after packet transmission.

The RX area is associated to the output of the RX FIFO of packets, and is used to access receive packet data and status information.

The logical address is specified by loading the

address pointer register. The pointer can automatically increment on accesses.

All accesses to the RAM are done via I/O space. A bit in the address pointer also specifies if the address refers to the TX or RX area.

In the TX area, the host CPU has access to the next transmit packet being prepared for transmission. In the RX area, it has access to the first receive packet not processed by the CPU yet.

The FIFO of packets, existing beneath the TX and RX areas, is managed by the MMU. The MMU dynamically allocates and releases memory to be used by the transmit and receive functions.

The MMU related parameters for the SMC91C95 are:

RAM size	6 kbytes (internal)
Max. number of packets	24
Max. pages per packet	6
Max. number of pages	24
Page size	256 bytes