Int | SMC Networks SMC91C95 guide

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FIGURE 9 - INTERRUPT STRUCTURE

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Image 64

SMC Networks SMC91C95 manual Int

Contents

Features Bus Interface Table of Contents Network Interface PIN ConfigurationSoftware Drivers General Description OverviewPage ISA Uses non-volatile jumperless setup via serial EepromPcmcia Function ISA Pcmcia Number Pins PIN Requirements Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GND Total PinsRecp Coln PIN no Name Symbol Type Description Description of PIN Functions ISA Byte High Enable input. Asserted low Pcmcia Card Enable 2 input. Used toEnable Select card on odd byte accesses Ready Reset Application of the VCC or Reset which ever ISA Output. Active high interrupt signal.Value of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not Whenever the SMC91C95 is in 16 bit mode Enable Function bit in the EcorIs with Input. Active low read strobe used to access Interrupt pin if enabled Pin is active high when either the Pwrdwn Output B Powerdown mode Pwrdwn bit is zeroValue of the Mringin input. When entering Pin when enabled by the Audio bit Modem Eeprom Eesk Eeprom EecsEeprom Eedo Sdout Eeprom Rxclk TXDRegister AUI TPE Tpetxdp Tperxn TPE TpetxpTxclk Endec VSSAvss Buffer Types SMC91C95 SMC91C95 SMC91C95 Internal Block Diagram BIT Mode Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15Functional Description Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15 Even byte IOis8=1 + nEN16=1.16BIT=0No Cycle Even byte SMC91C95 Address Spaces Signals ISA Pcmci ON-CHIP Depth Width UsedROM Buffer Memory Mapping and Paging VS. Receive and TX Area TX Completion CPU Side TX FifoFifo Receive Queue and Mapping Block Diagram SMC91C95Internal With Packet Format in Buffer Memory Transmit Packet Receive Packet ODD ODD CRCByte before the Control Byte should be ignored Receive Frame Status Word Address Hash Value Multicast Table BIT Function Pcmcia Mode ISA Mode Interrupt Output NIREQ when either function isInterrupt Structure SMC91C95 Interrupt Merging Reset Logic Reset FunctionsEcor Mcor Powerdown Logic Powerdown FunctionsPowerdown Powers Does not Entered Exited Power Down Pwrdwn Pcmcia Configuration Registers Address 8000-803Eh Pcmcia Attribute Memory Address 0- 7FFEh Attribute Memory Address Using Serial Eeprom 7FFEh 8000h 803Eh ISA and Pcmcia Mode TypesymbolSpace Offsetname Internal I/O Space Mapping BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 Bank Select Register Offset Name Type Symbol READ/WRITE BSR High Byte LOW BS2BS0 BS2 BS1 BS0 BANK# High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet LOW Pade Forco Loop Txena Byte Transmits AUI Fdse Fduplx Ephloop Loop Loops AT Network High Link CTR EXC Lost Latcol Wakeu Byte OvrnCarr LOW LTX Sqet LTX MULPage High Soft Strip Rxen Byte RST CARLOW Almul Prms Byte Abort Rxabort RxovrnintPage Memory Size Actual Memory Register FFH Space BANK0 Offset Name Type Symbol Memory Configuration MCRRegister READ/WRITE Device High Full SET AUI Byte Wait Step SelecDIS INT Byte INT SEL1 INT SEL0 Interrupt PIN Used A15 A14 A13 Byte LOW ROM SizeRA17 RA15 RA14 High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte High RCV Release LOW Eeprom Reload Store Byte EnableWakeu Auto Byte BAD Pcmcia Eeprom to Sram Memory Map 3FA 3FC3FD 3FF High Byte LOW Command N0/BUS Command SET xyzBusy Bit Readable 000 0 Noop no Operation Command Sequencing This register is updated upon an Allocate Memory MMU command Failed Allocated Packet NumberPage Page Through Ah Space BANK2 Offset Name Type SymbolData Register READ/WRITE Data High Data LOW Ercv EPH INT Rxovr Alloc TX INT RCV INT Empty Ercv INT Rxovr Empty TX INTPage INT LOW Multicast Table Byte High NXNDE IOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDOMDOE=0 MDOE=1 Bit MDO High Byte LOW Byte Chip REV Chip ID Value Device High Byte LOW RCV Byte Discr Memory Architecture Theory of OperationFull Duplex Ethernet Support Behavior in Fdse Mode Main 802.3 section affected by Fdse is Typical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine CSMA/CD MMU RAM RX Intr TX Intr Assumes Auto Release Option Selected Txempty Intr Driver Send and Allocate Routines Memory Partitioning Interrupt Generation Internal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Pcmcia Configuration Registers Description SresetWrattri Ireq 8002h Ethernet Configuration and Status Register Ecsr IOIs8Page LevIREQ Enable Pcmcia functionality, this bit must be set IOIs8 Reserved Audio 8024h Pin Replacement Register PRR Current Value Value Written NEW Value Ringevent Ringenable 8028h Extended Status RegisterESR 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register A15 A14 A13 A12 A11 A10 8032h Modem I/O Size Register Memory Management Unit Functional Description of the BlocksArbiter BUS Interface Wait State Policy DMA Block Packet Number Fifos DMA MMU Packet Number Flow and Relevant Registers Csma Block Network Interface 10BASE-TAUI Physical Interface Transmit Functions Receive Functions Page Board Setup Information ISA Mode Ethernet Individual Address I/O Base AddressEeprom Word Register Address Diagnostic LEDs Arbitration ConsiderationsPage 64 X 16 Serial Eeprom MAP for ISA Mode 103 Operational Description Maximum Guaranteed RatingsParameter Symbo MIN TYP MAX Units Comments Input Leakage IP Type BuffersID Type Buffers Type Buffer OD16 Type Buffer OD162 Type BufferOD24 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test Condition Capacitive Load on Outputs Parameter MIN TYP MAX UnitsINTRO-INTR3 Timing Diagrams A50, nREG NCE1 NOE D150 30 max Max MinData Valid 108 NWE High NCE1 Low to nWE High Setup Address/nREG Setup Time to NWE Low109 O Read Timing Table on the following 110 Parameter Min Typ Max Units O Write Timing Table on the following 112 100 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 114 NINPAC 115 Consecutive Pcmcia Write Cycles 116 Pcmcia Attribute Memory READ/WRITE A15=0 117 Mringoutb 118 ISA Consecutive Read Cycles 119 ISA Consecutive Write Cycles 120 ISA Consecutive Read and Write Cycles 121 Data Register Special Read Access 122 Data Register Special Write Access 123 BIT Mode Register Cycles 124 ISA Register Access When Using Bale 125 External ROM Read Access Using Bale 126 Eeprom Read 127 Eeprom Write 128 Memory Read Timing 129 External Endec Interface Start of Transmit 130 Differential Output Signal Timing 10BASE-T and AUI 131 Recp Recn Tperxpn Tperxp Tperxn Recp Recn Transmit Timing END of Frame AUI and 10BASE-T 134 Collision Timing AUI 135 Vtqfp Package Outline 136Page Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516