THEORY OF OPERATION
PC Card 5.0 treats the individual functions of a
multifunction PCMCIA application independently. Card and Socket Services (C&SS) 5.0 is designed to provide the support for determining the function generating the interrupt and informing relevant drivers. The registers for the two functions are treated as independent sets. One of the only requirements is to set the functions’ I/O base registers with different values to avoid any access conflict.
MEMORY ARCHITECTURE
The concept of presenting the shared RAM as FIFO of packets, with a memory management unit allocating memory on a per packet basis responds to the following needs:
Memory allocation for receive vs. transmit - A fixed partition between receive and transmit area would not be efficient. Being able to dynamically allocate it to transmit and receive represents almost the equivalent of duplicating the memory size for some workstation type of drivers.
Software overhead - By presenting a FIFO of packets, the software driver does not have to waste any time in calculating pointers for the different buffers that make up different packets. The driver usually deals with one packet at a
time. With this approach, packets are accessible always at the same fixed address, and access is provided to any byte of the packet.
Headers can be analyzed without reading out the entire packet. The packet can be moved in or out with a block move operation.
Multiple upper layer support - The SMC91C95 facilitates interfacing to multiple upper layer protocols because of the receive packet
processing flexibility. A receive lookahead scheme like ODI or NDIS drivers is supported by copying a small part of the received packet and letting the upper layer provide a pointer for the rest of the data. If the upper layer indicates it does not want a specific part of the packet, a block move operation starting at any particular offset can be done. Out of order receive processing is also supported: if memory for one packet is not yet available, receive packet processing can continue.
Efficiency - Lacking any level of indirection or linked lists of pointers, virtually all the memory is used for data. There are not descriptors, forward links and pointers at all. This simplicity and memory efficiency is accomplished without giving up the benefits of linked lists which is unlimited
FULL DUPLEX ETHERNET SUPPORT
Full Duplex Ethernet operation refers to the ability of the network (or parts of it) to simultaneously transmit and receive packets. The CSMA/CD protocol used by Ethernet for accessing a shared medium is inherently half duplex , and so is the
The SMC91C95 supports two types of Full Duplex operation:
1.Full Duplex mode for diagnostic purposes only, where the received packet is the transmit packet being looped back. This mode is enabled using the FDUPLX bit in the TCR. In this mode the CSMA/CD algorithm is used to gain access to the media.
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