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FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH
BUS IN TERFAC E
ARBIT ER
MMU
BUFFE R RA M
CSMA /CD
ENDE C
TWIST ED PAIR
TRAN SCEIV ER
AUI
10BAS ET
DATA BUS
ADDR ESS
BUS
CONT ROL
EEPRO M
EEPRO M
WRITE
DATA
REG.
READ
DATA
REG.
TX
FIFO
TX
COMP L
FIFO
RX
FIFO DM A
INTER FACE
ADDR ESSDATA