54
CR ENABLE - Counter Roll over Enable. When
set it enables the CTR_ROL bit as one of the
interrupts merged into the EPH INT bit. Defaults
low (disabled).
TE ENABLE - Transmit Error Enable. When set it
enables Transmit Error as one of the interrupts
merged into the EPH INT bit. Defaults low
(disabled). Transmit Error is any condition that
clears TXENA with TX_SUC staying low as
described in the EPHSR register.
EEPROM SELECT - This bit allows the CPU to
specify which registers the EEPROM RELOAD or
STORE refers to. When high, the General Purpose
Register is the only register read or written. When
low, the RELOAD and STORE functions are
enabled.
RELOAD
In ISA Mode: The SMC91C95 reads the
Configuration, Base and Individual Address,
and STORE writes the Configuration and Base
registers. Also when set it will read the
EEPROM and update relevant registers with its
contents. This bit then Clears upon completing
the operation.
In PCMCIA Mode: The SMC91C95 reads the
contents of the EEPROM and stores the
contents in the SMC91C95 CIS SRAM as
defined in Table 10.
STORE
In ISA Mode: The STORE bit when set, stores
the contents of all relevant registers in the serial
EEPROM. This bit is cleard upon completing
the operation.
In PCMCIA Mode: The SMC91C95 performs
no function.
NOTE: When an EEPROM access is in progress
the STORE and RELOAD bits will be read back as
high. The remaining 14 bits of this register will be
invalid. During this time, attempted read/write
operations, other than polling the EEPROM status,
will NOT have any effect on the internal registers.
The CPU can resume accesses to the SMC91C95
after both bits are low. A worst case RELOAD
operation initiated by RESET or by software takes
less than 750 µsec.
PCMCIA EEPROM to SRAM Memory Map
As defined in the PCMCIA specification, Odd byte
attribute memory locations are a don’t care. In
order to utilize the serial EEPROM and internal
SMC91C95 SRAM, the data to memory mapping
is shown in Table 10.