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SMC Networks SMC91C95 manual ISA Register Access When Using Bale, 125

Models: SMC91C95

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AEN

A0-15, nSBHE

BALE

nIOCS16

nIORD nIOWR

VALID

t15

	Parameter	min	typ	max	units

t1	Address, nSBHE Setup to BALE Falling	20			ns
t2	Address, nSBHE Hold after BALE Falling	20			ns
t3	Address, nSBHE, AEN Setup to Control Active	25			ns
t4	AEN Hold after Control Inactive	20			ns
t15	A4-A15, AEN Low, BALE High to nIOCS16 Low			25	ns

t4 not needed. nIOCS16 not relevant in 8-bit mode.

FIGURE 34 - ISA REGISTER ACCESS WHEN USING BALE

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Page 125

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SMC Networks SMC91C95 manual ISA Register Access When Using Bale, 125

Contents

Bus Interface FeaturesTable of Contents Software Drivers PIN ConfigurationNetwork Interface Overview General DescriptionPage Pcmcia Uses non-volatile jumperless setup via serial EepromISA PIN Requirements Function ISA Pcmcia Number PinsTotal Pins Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GNDRecp ColnDescription of PIN Functions PIN no Name Symbol Type DescriptionPcmcia Card Enable 2 input. Used to ISA Byte High Enable input. Asserted lowEnable Select card on odd byte accesses Ready ResetISA Output. Active high interrupt signal. Application of the VCC or Reset which everValue of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when notEnable Function bit in the Ecor Whenever the SMC91C95 is in 16 bit modeIs with Input. Active low read strobe used to access Interrupt pin if enabledOutput B Powerdown mode Pwrdwn bit is zero Pin is active high when either the PwrdwnValue of the Mringin input. When entering Pin when enabled by the Audio bit ModemEeprom Eecs Eeprom EeskEeprom Eedo Sdout EepromTXD RxclkRegister AUITxclk Tperxn TPE TpetxpTPE Tpetxdp VSS EndecAvss Buffer TypesSMC91C95 SMC91C95 SMC91C95 Internal Block Diagram Functional Description Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15BIT Mode Even byte IOis8=1 + nEN16=1.16BIT=0 Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15No Cycle Even byteROM Signals ISA Pcmci ON-CHIP Depth Width UsedSMC91C95 Address Spaces Buffer Memory Mapping and Paging VS. Receive and TX Area Fifo CPU Side TX FifoTX Completion Receive Queue and Mapping SMC91C95 Block DiagramInternal WithTransmit Packet Receive Packet Packet Format in Buffer MemoryByte before the Control Byte should be ignored ODD CRCODD Address Hash Value Multicast Table BIT Receive Frame Status WordInterrupt Output NIREQ when either function is Function Pcmcia Mode ISA ModeInterrupt Structure SMC91C95 Interrupt MergingReset Functions Reset LogicEcor McorPowerdown Functions Powerdown LogicPowerdown Powers Does not Entered Exited Power Down PwrdwnPcmcia Attribute Memory Address 0- 7FFEh Pcmcia Configuration Registers Address 8000-803Eh7FFEh 8000h 803Eh Attribute Memory Address Using Serial EepromTypesymbol ISA and Pcmcia ModeSpace OffsetnameBANK0 BANK1 BANK2 BANK3 BANK4 BANK5 Internal I/O Space MappingHigh Byte LOW BS2 Bank Select Register Offset Name Type Symbol READ/WRITE BSRBS0 BS2 BS1 BS0 BANK#LOW Pade Forco Loop Txena Byte High Fdse EPH STP Fdupl MON Nocrc Byte Loop SqetAUI Fdse Fduplx Ephloop Loop Loops AT Network TransmitsOvrn High Link CTR EXC Lost Latcol Wakeu ByteCarr LOW LTX Sqet LTX MULPage Strip Rxen Byte RST CAR High SoftLOW Almul Prms Byte Abort Rxabort RxovrnintPage FFH Memory Size Actual Memory RegisterMCR Space BANK0 Offset Name Type Symbol Memory ConfigurationRegister READ/WRITE DeviceSelec High Full SET AUI Byte Wait StepDIS INT ByteINT SEL1 INT SEL0 Interrupt PIN Used Byte LOW ROM Size A15 A14 A13RA17 RA15 RA14High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte Wakeu Auto Byte BAD Release LOW Eeprom Reload Store Byte EnableHigh RCV Pcmcia Eeprom to Sram Memory Map 3FC 3FA3FD 3FFCommand SET xyz High Byte LOW Command N0/BUSBusy Bit Readable 000 0 Noop no OperationCommand Sequencing Failed Allocated Packet Number This register is updated upon an Allocate Memory MMU commandPage Page Data Register READ/WRITE Data High Data LOW Space BANK2 Offset Name Type SymbolThrough Ah Ercv INT Rxovr Empty TX INT Ercv EPH INT Rxovr Alloc TX INT RCV INT EmptyPage INT LOW Multicast Table Byte High IOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO NXNDEMDOE=0 MDOE=1 Bit MDOChip ID Value Device High Byte LOW Byte Chip REVByte Discr High Byte LOW RCVFull Duplex Ethernet Support Theory of OperationMemory Architecture Main 802.3 section affected by Fdse is Behavior in Fdse ModeTypical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine MMU RAM CSMA/CDRX Intr Assumes Auto Release Option Selected TX IntrTxempty Intr Driver Send and Allocate Routines Interrupt Generation Memory PartitioningInternal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Sreset Pcmcia Configuration Registers DescriptionWrattri IreqIOIs8 8002h Ethernet Configuration and Status Register EcsrPage Pcmcia functionality, this bit must be set LevIREQ EnableIOIs8 Reserved Audio Current Value Value Written NEW Value 8024h Pin Replacement Register PRR8028h Extended Status RegisterESR Ringevent RingenableA15 A14 A13 A12 A11 A10 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register8032h Modem I/O Size Register Arbiter Functional Description of the BlocksMemory Management Unit Wait State Policy BUS InterfaceDMA Block Packet Number Fifos MMU Packet Number Flow and Relevant Registers DMACsma Block 10BASE-T Network InterfaceAUI Physical InterfaceTransmit Functions Receive Functions Page Ethernet Individual Address I/O Base Address Board Setup Information ISA ModeEeprom Word Register AddressArbitration Considerations Diagnostic LEDsPage 103 64 X 16 Serial Eeprom MAP for ISA ModeParameter Symbo MIN TYP MAX Units Comments Maximum Guaranteed RatingsOperational Description IP Type Buffers Input LeakageID Type Buffers Type BufferOD162 Type Buffer OD16 Type BufferOD24 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test ConditionINTRO-INTR3 Parameter MIN TYP MAX UnitsCapacitive Load on Outputs A50, nREG NCE1 NOE D150 30 max Max Min Timing DiagramsData Valid 108109 Address/nREG Setup Time to NWE LowNWE High NCE1 Low to nWE High Setup 110 O Read Timing Table on the followingParameter Min Typ Max Units 112 O Write Timing Table on the following100 114 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1115 NINPAC116 Consecutive Pcmcia Write Cycles117 Pcmcia Attribute Memory READ/WRITE A15=0118 Mringoutb119 ISA Consecutive Read Cycles120 ISA Consecutive Write Cycles121 ISA Consecutive Read and Write Cycles122 Data Register Special Read Access123 Data Register Special Write Access124 BIT Mode Register Cycles125 ISA Register Access When Using Bale126 External ROM Read Access Using Bale127 Eeprom Read128 Eeprom Write129 Memory Read Timing130 External Endec Interface Start of Transmit131 Differential Output Signal Timing 10BASE-T and AUITperxpn Recp RecnTperxp Tperxn Recp Recn 134 Transmit Timing END of Frame AUI and 10BASE-T135 Collision Timing AUI136 Vtqfp Package OutlinePage Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516