Powerdown Logic, Powerdown Functions | SMC Networks SMC91C95

POWERDOWN LOGIC

The pins and bits involved in powerdown are:

1.PWRDWN/TXCLK - Input pin valid when XENDEC is not zero (0).

2.Pwrdwn bits in ECSR and MCSR registers - One bit for each function

3.Enable Function bits in ECOR and MCOR registers - One bit for each function

4.PWRDN - Ethernet powerdown bit in Control Register.

5.WAKUP_EN - Magic packet receive enable bit in the Control Register

6.nWAKEUP - Pin for Magic Packet receive + Ethernet function powerdown

SMC91C95 Powerdown States:

A)The SMC91C95 is Off and no Clock is running

B1) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with No Link Pulses for LAN access

B2) The SMC91C95 of Off with clock running (No Active LAN or Host Data Transfer) TBD Current Reduction with Link active

C)The SMC91C95 is completely powered up (With Active LAN or Host Data transfer) 80MA Max, 40MA typ.

	Table 6 - Powerdown Functions

	POWERDOWN	POWERDOWN	POWERS	DOES NOT
	ENTERED	EXITED	POWERS	POWER DOWN
			DOWN:

(A) PWRDWN/	When pin is high	When pin goes	Ethernet Function
TXCLK Pin	and reset is	low	including Link
	inactive		circuitry; Modem
			Function

(B1) ECOR and	Pwrdwn bit in	Otherwise, or	Ethernet Function	Modem function,
ECSR Powerdown	ECSR is high or	when function is	plus any analog	Attribute Memory
Bits	Enable Function bit	reset in ISA	logic including link	and PCMCIA
	in ECOR is low.	mode	logic	Configuration
				Registers access

(B2) Power State	Pwrdwn bit in	Otherwise; or	Modem	Ethernet function,
MCOR and MCSR	MCSR is high or	Ringing from		Attribute Memory
Bits	Enable Function bit	modem chipset		and PCMCIA
	in MCOR is low.			Configuration
				Registers access

(B2) Power State	Pwrdwn bit in	Magic Packet	Ethernet MAC	Modem Function,
WAKUP_EN	ECSR is high or	received	logic (Link is	Attribute memory
(Control Register)	Enable Function bit	(WAKUP in EPH	enabled)	and PCMCIA
	in ECOR is low or	status)		configuration
	PWRDN bit in			Registers access,
	Control Register is			Link Logic
	high

		34

Image 34

SMC Networks SMC91C95 Powerdown Logic, Powerdown Functions, Powerdown Powers Does not Entered Exited Power Down, Pwrdwn

Contents

Features Bus Interface Table of Contents Network Interface PIN ConfigurationSoftware Drivers General Description OverviewPage ISA Uses non-volatile jumperless setup via serial EepromPcmcia Function ISA Pcmcia Number Pins PIN Requirements Recp Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GNDTotal Pins Coln PIN no Name Symbol Type Description Description of PIN Functions Enable Select card on odd byte accesses Ready ISA Byte High Enable input. Asserted lowPcmcia Card Enable 2 input. Used to Reset Value of INT SEL1-0 bits in the Configuration Application of the VCC or Reset which everISA Output. Active high interrupt signal. Register. This interrupt is tri-stated when not Is with Input. Active low read strobe used to access Whenever the SMC91C95 is in 16 bit modeEnable Function bit in the Ecor Interrupt pin if enabled Value of the Mringin input. When entering Pin is active high when either the PwrdwnOutput B Powerdown mode Pwrdwn bit is zero Pin when enabled by the Audio bit Modem Eeprom Eedo Eeprom EeskEeprom Eecs Sdout Eeprom Register RxclkTXD AUI TPE Tpetxdp Tperxn TPE TpetxpTxclk Avss EndecVSS Buffer Types SMC91C95 SMC91C95 SMC91C95 Internal Block Diagram BIT Mode Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15Functional Description No Cycle Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15Even byte IOis8=1 + nEN16=1.16BIT=0 Even byte SMC91C95 Address Spaces Signals ISA Pcmci ON-CHIP Depth Width UsedROM Buffer Memory Mapping and Paging VS. Receive and TX Area TX Completion CPU Side TX FifoFifo Receive Queue and Mapping Internal Block DiagramSMC91C95 With Packet Format in Buffer Memory Transmit Packet Receive Packet ODD ODD CRCByte before the Control Byte should be ignored Receive Frame Status Word Address Hash Value Multicast Table BIT Interrupt Structure Function Pcmcia Mode ISA ModeInterrupt Output NIREQ when either function is SMC91C95 Interrupt Merging Ecor Reset LogicReset Functions Mcor Powerdown Powers Does not Entered Exited Power Down Powerdown LogicPowerdown Functions Pwrdwn Pcmcia Configuration Registers Address 8000-803Eh Pcmcia Attribute Memory Address 0- 7FFEh Attribute Memory Address Using Serial Eeprom 7FFEh 8000h 803Eh Space ISA and Pcmcia ModeTypesymbol Offsetname Internal I/O Space Mapping BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BS0 Bank Select Register Offset Name Type Symbol READ/WRITE BSRHigh Byte LOW BS2 BS2 BS1 BS0 BANK# High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet LOW Pade Forco Loop Txena Byte Transmits AUI Fdse Fduplx Ephloop Loop Loops AT Network Carr LOW LTX Sqet High Link CTR EXC Lost Latcol Wakeu ByteOvrn LTX MULPage LOW Almul Prms Byte Abort High SoftStrip Rxen Byte RST CAR Rxabort RxovrnintPage Memory Size Actual Memory Register FFH Register READ/WRITE Space BANK0 Offset Name Type Symbol Memory ConfigurationMCR Device DIS High Full SET AUI Byte Wait StepSelec INT Byte INT SEL1 INT SEL0 Interrupt PIN Used RA17 A15 A14 A13Byte LOW ROM Size RA15 RA14 High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte High RCV Release LOW Eeprom Reload Store Byte EnableWakeu Auto Byte BAD Pcmcia Eeprom to Sram Memory Map 3FD 3FA3FC 3FF Busy Bit Readable High Byte LOW Command N0/BUSCommand SET xyz 000 0 Noop no Operation Command Sequencing This register is updated upon an Allocate Memory MMU command Failed Allocated Packet NumberPage Page Through Ah Space BANK2 Offset Name Type SymbolData Register READ/WRITE Data High Data LOW Ercv EPH INT Rxovr Alloc TX INT RCV INT Empty Ercv INT Rxovr Empty TX INTPage INT LOW Multicast Table Byte High MDOE=0 MDOE=1 NXNDEIOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO Bit MDO High Byte LOW Byte Chip REV Chip ID Value Device High Byte LOW RCV Byte Discr Memory Architecture Theory of OperationFull Duplex Ethernet Support Behavior in Fdse Mode Main 802.3 section affected by Fdse is Typical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine CSMA/CD MMU RAM RX Intr TX Intr Assumes Auto Release Option Selected Txempty Intr Driver Send and Allocate Routines Memory Partitioning Interrupt Generation Internal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Wrattri Pcmcia Configuration Registers DescriptionSreset Ireq 8002h Ethernet Configuration and Status Register Ecsr IOIs8Page LevIREQ Enable Pcmcia functionality, this bit must be set IOIs8 Reserved Audio 8024h Pin Replacement Register PRR Current Value Value Written NEW Value Ringevent Ringenable 8028h Extended Status RegisterESR 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register A15 A14 A13 A12 A11 A10 8032h Modem I/O Size Register Memory Management Unit Functional Description of the BlocksArbiter BUS Interface Wait State Policy DMA Block Packet Number Fifos DMA MMU Packet Number Flow and Relevant Registers Csma Block AUI Network Interface10BASE-T Physical Interface Transmit Functions Receive Functions Page Eeprom Word Board Setup Information ISA ModeEthernet Individual Address I/O Base Address Register Address Diagnostic LEDs Arbitration ConsiderationsPage 64 X 16 Serial Eeprom MAP for ISA Mode 103 Operational Description Maximum Guaranteed RatingsParameter Symbo MIN TYP MAX Units Comments ID Type Buffers Input LeakageIP Type Buffers Type Buffer OD24 Type Buffer OD16 Type BufferOD162 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test Condition Capacitive Load on Outputs Parameter MIN TYP MAX UnitsINTRO-INTR3 Data Valid Timing DiagramsA50, nREG NCE1 NOE D150 30 max Max Min 108 NWE High NCE1 Low to nWE High Setup Address/nREG Setup Time to NWE Low109 O Read Timing Table on the following 110 Parameter Min Typ Max Units O Write Timing Table on the following 112 100 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 114 NINPAC 115 Consecutive Pcmcia Write Cycles 116 Pcmcia Attribute Memory READ/WRITE A15=0 117 Mringoutb 118 ISA Consecutive Read Cycles 119 ISA Consecutive Write Cycles 120 ISA Consecutive Read and Write Cycles 121 Data Register Special Read Access 122 Data Register Special Write Access 123 BIT Mode Register Cycles 124 ISA Register Access When Using Bale 125 External ROM Read Access Using Bale 126 Eeprom Read 127 Eeprom Write 128 Memory Read Timing 129 External Endec Interface Start of Transmit 130 Differential Output Signal Timing 10BASE-T and AUI 131 Recp Recn Tperxpn Tperxp Tperxn Recp Recn Transmit Timing END of Frame AUI and 10BASE-T 134 Collision Timing AUI 135 Vtqfp Package Outline 136Page Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516