High RCV, Wakeu Auto Byte BAD | SMC Networks SMC91C95 specs

I/O SPACE - BANK1
OFFSET				NAME			TYPE		SYMBOL
C			CONTROL REGISTER				READ/WRITE		CTR

HIGH		0	RCV_		PWRDWN	WAKEU	AUTO			1
BYTE			BAD			P_EN	RELEASE

		0	0	0		0	0	X	X	1
LOW		LE	CR		TE			EEPROM	RELOAD	STORE
BYTE		ENABLE	ENABLE		ENABLE			SELECT
		0	0	0		X	X	0	0	0

RCV_BAD - When set, bad CRC packets are received. When clear bad CRC packets do not generate interrupts and their memory is released.

PWRDN - Active high bit used to put the Ethernet function in powerdown mode.

Cleared by:

1.A write to any register in the SMC91C95 I/O space

2.Hardware reset

3.“Magic Packet” was received

This bit is combined with the Pwrdwn bit in ECSR and with the powerdown bit to determine when the function is powered down.

WAKUP_EN - Active high bit used to enable the controller in any of the powerdown modes to power up if a “Magic Packet” is detected and set the WAKEUP bit in the EPHSR to generate an EPH interrupt (if not masked). When clear (0), no “Magic Packet” scanning is done on receive packets.

NOTE: If “Magic Packet” is enabled using this bit only the notification is done on the WAKEUP bit in the EPHSR only.

AUTO RELEASE - When set, transmit pages are released by transmit completion if the transmission was successful (when TX_SUC is set). In that case there is no status word associated with its packet number, and successful packet numbers are not even written into the TX COMPLETION FIFO. A sequence of transmit packets will only generate an interrupt when the sequence is completely transmitted (TX EMPTY INT will be set), or when a packet in the sequence experiences a fatal error (TX INT will be set).

Upon a fatal error TXENA is cleared and the transmission sequence stops. The packet number that failed is the present in the FIFO PORTS register, and its pages are not released, allowing the CPU to restart the sequence after corrective action is taken.

LE ENABLE - Link Error Enable. When set it enables the LINK_OK bit transition as one of the interrupts merged into the EPH INT bit. Defaults low (disabled). Writing this bit also serves as the acknowledge by clearing previous LINK interrupt conditions.

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SMC Networks SMC91C95 manual High RCV, Wakeu Auto Byte BAD, Release LOW Eeprom Reload Store Byte Enable

Contents

Bus Interface Features Table of Contents Software Drivers PIN ConfigurationNetwork Interface Overview General DescriptionPage Pcmcia Uses non-volatile jumperless setup via serial EepromISA PIN Requirements Function ISA Pcmcia Number Pins Total Pins Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GNDRecp Coln Description of PIN Functions PIN no Name Symbol Type Description Pcmcia Card Enable 2 input. Used to ISA Byte High Enable input. Asserted lowEnable Select card on odd byte accesses Ready Reset ISA Output. Active high interrupt signal. Application of the VCC or Reset which everValue of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not Enable Function bit in the Ecor Whenever the SMC91C95 is in 16 bit modeIs with Input. Active low read strobe used to access Interrupt pin if enabled Output B Powerdown mode Pwrdwn bit is zero Pin is active high when either the PwrdwnValue of the Mringin input. When entering Pin when enabled by the Audio bit Modem Eeprom Eecs Eeprom EeskEeprom Eedo Sdout Eeprom TXD RxclkRegister AUI Txclk Tperxn TPE TpetxpTPE Tpetxdp VSS EndecAvss Buffer Types SMC91C95 SMC91C95 SMC91C95 Internal Block Diagram Functional Description Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15BIT Mode Even byte IOis8=1 + nEN16=1.16BIT=0 Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15No Cycle Even byte ROM Signals ISA Pcmci ON-CHIP Depth Width UsedSMC91C95 Address Spaces Buffer Memory Mapping and Paging VS. Receive and TX Area Fifo CPU Side TX FifoTX Completion Receive Queue and Mapping SMC91C95 Block DiagramInternal With Transmit Packet Receive Packet Packet Format in Buffer Memory Byte before the Control Byte should be ignored ODD CRCODD Address Hash Value Multicast Table BIT Receive Frame Status Word Interrupt Output NIREQ when either function is Function Pcmcia Mode ISA ModeInterrupt Structure SMC91C95 Interrupt Merging Reset Functions Reset LogicEcor Mcor Powerdown Functions Powerdown LogicPowerdown Powers Does not Entered Exited Power Down Pwrdwn Pcmcia Attribute Memory Address 0- 7FFEh Pcmcia Configuration Registers Address 8000-803Eh 7FFEh 8000h 803Eh Attribute Memory Address Using Serial Eeprom Typesymbol ISA and Pcmcia ModeSpace Offsetname BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 Internal I/O Space Mapping High Byte LOW BS2 Bank Select Register Offset Name Type Symbol READ/WRITE BSRBS0 BS2 BS1 BS0 BANK# LOW Pade Forco Loop Txena Byte High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet AUI Fdse Fduplx Ephloop Loop Loops AT Network Transmits Ovrn High Link CTR EXC Lost Latcol Wakeu ByteCarr LOW LTX Sqet LTX MULPage Strip Rxen Byte RST CAR High SoftLOW Almul Prms Byte Abort Rxabort RxovrnintPage FFH Memory Size Actual Memory Register MCR Space BANK0 Offset Name Type Symbol Memory ConfigurationRegister READ/WRITE Device Selec High Full SET AUI Byte Wait StepDIS INT Byte INT SEL1 INT SEL0 Interrupt PIN Used Byte LOW ROM Size A15 A14 A13RA17 RA15 RA14 High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte Wakeu Auto Byte BAD Release LOW Eeprom Reload Store Byte EnableHigh RCV Pcmcia Eeprom to Sram Memory Map 3FC 3FA3FD 3FF Command SET xyz High Byte LOW Command N0/BUSBusy Bit Readable 000 0 Noop no Operation Command Sequencing Failed Allocated Packet Number This register is updated upon an Allocate Memory MMU commandPage Page Data Register READ/WRITE Data High Data LOW Space BANK2 Offset Name Type SymbolThrough Ah Ercv INT Rxovr Empty TX INT Ercv EPH INT Rxovr Alloc TX INT RCV INT EmptyPage INT LOW Multicast Table Byte High IOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO NXNDEMDOE=0 MDOE=1 Bit MDO Chip ID Value Device High Byte LOW Byte Chip REV Byte Discr High Byte LOW RCV Full Duplex Ethernet Support Theory of OperationMemory Architecture Main 802.3 section affected by Fdse is Behavior in Fdse Mode Typical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine MMU RAM CSMA/CD RX Intr Assumes Auto Release Option Selected TX Intr Txempty Intr Driver Send and Allocate Routines Interrupt Generation Memory Partitioning Internal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Sreset Pcmcia Configuration Registers DescriptionWrattri Ireq IOIs8 8002h Ethernet Configuration and Status Register EcsrPage Pcmcia functionality, this bit must be set LevIREQ Enable IOIs8 Reserved Audio Current Value Value Written NEW Value 8024h Pin Replacement Register PRR 8028h Extended Status RegisterESR Ringevent Ringenable A15 A14 A13 A12 A11 A10 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register 8032h Modem I/O Size Register Arbiter Functional Description of the BlocksMemory Management Unit Wait State Policy BUS Interface DMA Block Packet Number Fifos MMU Packet Number Flow and Relevant Registers DMA Csma Block 10BASE-T Network InterfaceAUI Physical Interface Transmit Functions Receive Functions Page Ethernet Individual Address I/O Base Address Board Setup Information ISA ModeEeprom Word Register Address Arbitration Considerations Diagnostic LEDsPage 103 64 X 16 Serial Eeprom MAP for ISA Mode Parameter Symbo MIN TYP MAX Units Comments Maximum Guaranteed RatingsOperational Description IP Type Buffers Input LeakageID Type Buffers Type Buffer OD162 Type Buffer OD16 Type BufferOD24 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test Condition INTRO-INTR3 Parameter MIN TYP MAX UnitsCapacitive Load on Outputs A50, nREG NCE1 NOE D150 30 max Max Min Timing DiagramsData Valid 108 109 Address/nREG Setup Time to NWE LowNWE High NCE1 Low to nWE High Setup 110 O Read Timing Table on the following Parameter Min Typ Max Units 112 O Write Timing Table on the following 100 114 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 115 NINPAC 116 Consecutive Pcmcia Write Cycles 117 Pcmcia Attribute Memory READ/WRITE A15=0 118 Mringoutb 119 ISA Consecutive Read Cycles 120 ISA Consecutive Write Cycles 121 ISA Consecutive Read and Write Cycles 122 Data Register Special Read Access 123 Data Register Special Write Access 124 BIT Mode Register Cycles 125 ISA Register Access When Using Bale 126 External ROM Read Access Using Bale 127 Eeprom Read 128 Eeprom Write 129 Memory Read Timing 130 External Endec Interface Start of Transmit 131 Differential Output Signal Timing 10BASE-T and AUI Tperxpn Recp Recn Tperxp Tperxn Recp Recn 134 Transmit Timing END of Frame AUI and 10BASE-T 135 Collision Timing AUI 136 Vtqfp Package OutlinePage Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516