Manuals
/
SMC Networks
/
Computer Equipment
/
Modem
SMC Networks
SMC91C95
manual
INT SEL1 INT SEL0 Interrupt PIN Used
Models:
SMC91C95
1
49
139
139
Download
139 pages
18.51 Kb
46
47
48
49
50
51
52
53
Block Diagram
Typesymbol
Warranty
PIN Configuration
Reset
Diagnostic LEDs
High Byte LOW Command N0/BUS
Total Pins
Powerdown Logic
Features
Page 49
Image 49
INT SEL1
INT SEL0
INTERRUPT PIN
USED
0
0
INTR0
0
1
INTR1
1
0
INTR2
1
1
INTR3
49
Page 48
Page 50
Page 49
Image 49
Page 48
Page 50
Contents
Bus Interface
Features
Table of Contents
Network Interface
PIN Configuration
Software Drivers
Overview
General Description
Page
ISA
Uses non-volatile jumperless setup via serial Eeprom
Pcmcia
PIN Requirements
Function ISA Pcmcia Number Pins
Total Pins
Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GND
Recp
Coln
Description of PIN Functions
PIN no Name Symbol Type Description
Pcmcia Card Enable 2 input. Used to
ISA Byte High Enable input. Asserted low
Enable Select card on odd byte accesses Ready
Reset
ISA Output. Active high interrupt signal.
Application of the VCC or Reset which ever
Value of INT SEL1-0 bits in the Configuration
Register. This interrupt is tri-stated when not
Enable Function bit in the Ecor
Whenever the SMC91C95 is in 16 bit mode
Is with Input. Active low read strobe used to access
Interrupt pin if enabled
Output B Powerdown mode Pwrdwn bit is zero
Pin is active high when either the Pwrdwn
Value of the Mringin input. When entering
Pin when enabled by the Audio bit Modem
Eeprom Eecs
Eeprom Eesk
Eeprom Eedo
Sdout Eeprom
TXD
Rxclk
Register
AUI
TPE Tpetxdp
Tperxn TPE Tpetxp
Txclk
VSS
Endec
Avss
Buffer Types
SMC91C95
SMC91C95
SMC91C95 Internal Block Diagram
BIT Mode
Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15
Functional Description
Even byte IOis8=1 + nEN16=1.16BIT=0
Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15
No Cycle
Even byte
SMC91C95 Address Spaces
Signals ISA Pcmci ON-CHIP Depth Width Used
ROM
Buffer Memory
Mapping and Paging VS. Receive and TX Area
TX Completion
CPU Side TX Fifo
Fifo
Receive Queue and Mapping
SMC91C95
Block Diagram
Internal
With
Transmit Packet Receive Packet
Packet Format in Buffer Memory
ODD
ODD CRC
Byte before the Control Byte should be ignored
Address Hash Value Multicast Table BIT
Receive Frame Status Word
Interrupt Output NIREQ when either function is
Function Pcmcia Mode ISA Mode
Interrupt Structure
SMC91C95 Interrupt Merging
Reset Functions
Reset Logic
Ecor
Mcor
Powerdown Functions
Powerdown Logic
Powerdown Powers Does not Entered Exited Power Down
Pwrdwn
Pcmcia Attribute Memory Address 0- 7FFEh
Pcmcia Configuration Registers Address 8000-803Eh
7FFEh 8000h 803Eh
Attribute Memory Address Using Serial Eeprom
Typesymbol
ISA and Pcmcia Mode
Space
Offsetname
BANK0 BANK1 BANK2 BANK3 BANK4 BANK5
Internal I/O Space Mapping
High Byte LOW BS2
Bank Select Register Offset Name Type Symbol READ/WRITE BSR
BS0
BS2 BS1 BS0 BANK#
LOW Pade Forco Loop Txena Byte
High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet
AUI Fdse Fduplx Ephloop Loop Loops AT Network
Transmits
Ovrn
High Link CTR EXC Lost Latcol Wakeu Byte
Carr LOW LTX Sqet
LTX MUL
Page
Strip Rxen Byte RST CAR
High Soft
LOW Almul Prms Byte Abort
Rxabort Rxovrnint
Page
FFH
Memory Size Actual Memory Register
MCR
Space BANK0 Offset Name Type Symbol Memory Configuration
Register READ/WRITE
Device
Selec
High Full SET AUI Byte Wait Step
DIS
INT Byte
INT SEL1 INT SEL0 Interrupt PIN Used
Byte LOW ROM Size
A15 A14 A13
RA17
RA15 RA14
High Address Byte LOW
High Byte LOW Byte High Data Byte LOW Data Byte
High RCV
Release LOW Eeprom Reload Store Byte Enable
Wakeu Auto Byte BAD
Pcmcia Eeprom to Sram Memory Map
3FC
3FA
3FD
3FF
Command SET xyz
High Byte LOW Command N0/BUS
Busy Bit Readable
000 0 Noop no Operation
Command Sequencing
Failed Allocated Packet Number
This register is updated upon an Allocate Memory MMU command
Page
Page
Through Ah
Space BANK2 Offset Name Type Symbol
Data Register READ/WRITE Data High Data LOW
Ercv INT Rxovr Empty TX INT
Ercv EPH INT Rxovr Alloc TX INT RCV INT Empty
Page
INT
LOW Multicast Table Byte High
IOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO
NXNDE
MDOE=0 MDOE=1
Bit MDO
Chip ID Value Device
High Byte LOW Byte Chip REV
Byte Discr
High Byte LOW RCV
Memory Architecture
Theory of Operation
Full Duplex Ethernet Support
Main 802.3 section affected by Fdse is
Behavior in Fdse Mode
Typical Flow of Events for Transmit Driver CSMA/CD Side
Typical Flow of Events for Receive Driver CSMA/CD Side
Ethernet Interrupt Service Routine
MMU RAM
CSMA/CD
RX Intr
Assumes Auto Release Option Selected
TX Intr
Txempty Intr
Driver Send and Allocate Routines
Interrupt Generation
Memory Partitioning
Internal VS. External Attribute Memory MAP
Attribute Memory Decodes Using Serial Eprom
Sreset
Pcmcia Configuration Registers Description
Wrattri
Ireq
IOIs8
8002h Ethernet Configuration and Status Register Ecsr
Page
Pcmcia functionality, this bit must be set
LevIREQ Enable
IOIs8 Reserved Audio
Current Value Value Written NEW Value
8024h Pin Replacement Register PRR
8028h Extended Status RegisterESR
Ringevent Ringenable
A15 A14 A13 A12 A11 A10
802Ah Modem I/O Base Register 802Ch Modem I/O Base Register
8032h Modem I/O Size Register
Memory Management Unit
Functional Description of the Blocks
Arbiter
Wait State Policy
BUS Interface
DMA Block
Packet Number Fifos
MMU Packet Number Flow and Relevant Registers
DMA
Csma Block
10BASE-T
Network Interface
AUI
Physical Interface
Transmit Functions Receive Functions
Page
Ethernet Individual Address I/O Base Address
Board Setup Information ISA Mode
Eeprom Word
Register Address
Arbitration Considerations
Diagnostic LEDs
Page
103
64 X 16 Serial Eeprom MAP for ISA Mode
Operational Description
Maximum Guaranteed Ratings
Parameter Symbo MIN TYP MAX Units Comments
IP Type Buffers
Input Leakage
ID Type Buffers
Type Buffer
OD162 Type Buffer
OD16 Type Buffer
OD24 Type Buffer
Limits Parameter Symbo MIN TYP MAX Unit Test Condition
Capacitive Load on Outputs
Parameter MIN TYP MAX Units
INTRO-INTR3
A50, nREG NCE1 NOE D150 30 max Max Min
Timing Diagrams
Data Valid
108
NWE High NCE1 Low to nWE High Setup
Address/nREG Setup Time to NWE Low
109
110
O Read Timing Table on the following
Parameter Min Typ Max Units
112
O Write Timing Table on the following
100
114
Card Configuration Registers READ/WRITE Pcmcia Mode A15=1
115
NINPAC
116
Consecutive Pcmcia Write Cycles
117
Pcmcia Attribute Memory READ/WRITE A15=0
118
Mringoutb
119
ISA Consecutive Read Cycles
120
ISA Consecutive Write Cycles
121
ISA Consecutive Read and Write Cycles
122
Data Register Special Read Access
123
Data Register Special Write Access
124
BIT Mode Register Cycles
125
ISA Register Access When Using Bale
126
External ROM Read Access Using Bale
127
Eeprom Read
128
Eeprom Write
129
Memory Read Timing
130
External Endec Interface Start of Transmit
131
Differential Output Signal Timing 10BASE-T and AUI
Tperxpn
Recp Recn
Tperxp Tperxn Recp Recn
134
Transmit Timing END of Frame AUI and 10BASE-T
135
Collision Timing AUI
136
Vtqfp Package Outline
Page
Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516
Top
Page
Image
Contents