TX INT bit - Set whenever the TX completion FIFO is not empty.
TX EMPTY INT bit - Set whenever the TX FIFO is empty.
AUTO RELEASE - When set, successful transmit packets are not written into completion FIFO, and their memory is released automatically.
1)One interrupt per packet: enable TX INT, set AUTO RELEASE=0. The software driver can find the completion result in memory and process the interrupt one packet at a time. Depending on the completion code the driver will take different actions. Note that the transmit process is working in parallel and other transmissions might be taking place. The SMC91C95 is virtually queuing the packet numbers and their status words.
In this case, the transmit interrupt service routine can find the next packet number to be serviced by reading the TX DONE PACKET NUMBER at the FIFO PORTS register. This eliminates the need for the driver to keep a list of packet numbers being transmitted. The numbers are queued by the SMC91C95 and provided back to the CPU as their transmission completes.
2)One interrupt per sequence of packets: Enable TX EMPTY INT and TX INT, set AUTO RELEASE=1. TX EMPTY INT is generated only after transmitting the last packet in the FIFO.
TX INT will be set on a fatal transmit error allowing the CPU to know that the transmit process has stopped and therefore the FIFO will not be emptied.
This mode has the advantage of a smaller CPU overhead, and faster memory de-
allocation. Note that when AUTO RELEASE=1
80
the CPU is not provided with the packet numbers that completed successfully.
NOTE: The pointer register is shared by any process accessing the SMC91C95 memory. In order to allow processes to be interruptable, the interrupting process is responsible for reading the pointer value before modifying it, saving it, and restoring it before returning from the interrupt.
Typically there would be three processes using the pointer:
1)Transmit loading (sometimes interrupt driven)
2)Receive unloading (interrupt driven)
3)Transmit Status reading (interrupt driven)
1)and 3) also share the usage of the Packet Number Register. Therefore saving and restoring the PNR is also required from interrupt service routines.
INTERNAL VS. EXTERNAL ATTRIBUTE MEMORY MAP
The Internal vs. External EPROM attribute memory decodes are shown in Table 11 and Table 12. This allows the designer to not require an external EPROM device if the single or multi- function PCMCIA card needs less than 512 bytes of configuration information. As can be seen in the map, if 512 bytes of CIS or less is required, the nFCS and nFWE output pins of the SMC91C95 need not be used (if serial EEPROM is being used). Internal to the SMC91C95, the memory addressing logic will allow byte or word access on even byte boundaries. This implies that on odd byte address access (A0=1), the SMC91C95 will generate a arbitrary value of Zero (0) since the PCMCIA specification states that the high byte of a word access in attribute memory is a don’t care. This allows backward compatibility to 8 bit hosts.
