CPU Side TX Fifo, TX Completion | SMC Networks SMC91C95 instruction

PACKET NUMBER
REGISTER
		STATUS	MEMORY
		COUNT	MEMORY
		COUNT
	PACKET #A		B
		DATA	B
CPU
SIDE	TX FIFO
		STATUS	A
		COUNT
	PACKET #B	DATA	C
			C
		TO
	CSMA		B
			B
TX COMPLETION		STATUS
FIFO		COUNT
	PACKET #C		C
		DATA	C
FIFO PORTS
REGISTER		LINEAR ADDRESS	MMU MAPPING
		LINEAR ADDRESS	MMU MAPPING

FIGURE 5 - TRANSMIT QUEUES AND MAPPING

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Image 26

SMC Networks SMC91C95 manual CPU Side TX Fifo, TX Completion

Contents

Features Bus Interface Table of Contents Software Drivers PIN ConfigurationNetwork Interface General Description OverviewPage Pcmcia Uses non-volatile jumperless setup via serial EepromISA Function ISA Pcmcia Number Pins PIN Requirements Recp Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GNDTotal Pins Coln PIN no Name Symbol Type Description Description of PIN Functions Enable Select card on odd byte accesses Ready ISA Byte High Enable input. Asserted lowPcmcia Card Enable 2 input. Used to Reset Value of INT SEL1-0 bits in the Configuration Application of the VCC or Reset which everISA Output. Active high interrupt signal. Register. This interrupt is tri-stated when not Is with Input. Active low read strobe used to access Whenever the SMC91C95 is in 16 bit modeEnable Function bit in the Ecor Interrupt pin if enabled Value of the Mringin input. When entering Pin is active high when either the PwrdwnOutput B Powerdown mode Pwrdwn bit is zero Pin when enabled by the Audio bit Modem Eeprom Eedo Eeprom EeskEeprom Eecs Sdout Eeprom Register RxclkTXD AUI Txclk Tperxn TPE TpetxpTPE Tpetxdp Avss EndecVSS Buffer Types SMC91C95 SMC91C95 SMC91C95 Internal Block Diagram Functional Description Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15BIT Mode No Cycle Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15Even byte IOis8=1 + nEN16=1.16BIT=0 Even byte ROM Signals ISA Pcmci ON-CHIP Depth Width UsedSMC91C95 Address Spaces Buffer Memory Mapping and Paging VS. Receive and TX Area Fifo CPU Side TX FifoTX Completion Receive Queue and Mapping Internal Block DiagramSMC91C95 With Packet Format in Buffer Memory Transmit Packet Receive Packet Byte before the Control Byte should be ignored ODD CRCODD Receive Frame Status Word Address Hash Value Multicast Table BIT Interrupt Structure Function Pcmcia Mode ISA ModeInterrupt Output NIREQ when either function is SMC91C95 Interrupt Merging Ecor Reset LogicReset Functions Mcor Powerdown Powers Does not Entered Exited Power Down Powerdown LogicPowerdown Functions Pwrdwn Pcmcia Configuration Registers Address 8000-803Eh Pcmcia Attribute Memory Address 0- 7FFEh Attribute Memory Address Using Serial Eeprom 7FFEh 8000h 803Eh Space ISA and Pcmcia ModeTypesymbol Offsetname Internal I/O Space Mapping BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BS0 Bank Select Register Offset Name Type Symbol READ/WRITE BSRHigh Byte LOW BS2 BS2 BS1 BS0 BANK# High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet LOW Pade Forco Loop Txena Byte Transmits AUI Fdse Fduplx Ephloop Loop Loops AT Network Carr LOW LTX Sqet High Link CTR EXC Lost Latcol Wakeu ByteOvrn LTX MULPage LOW Almul Prms Byte Abort High SoftStrip Rxen Byte RST CAR Rxabort RxovrnintPage Memory Size Actual Memory Register FFH Register READ/WRITE Space BANK0 Offset Name Type Symbol Memory ConfigurationMCR Device DIS High Full SET AUI Byte Wait StepSelec INT Byte INT SEL1 INT SEL0 Interrupt PIN Used RA17 A15 A14 A13Byte LOW ROM Size RA15 RA14 High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte Wakeu Auto Byte BAD Release LOW Eeprom Reload Store Byte EnableHigh RCV Pcmcia Eeprom to Sram Memory Map 3FD 3FA3FC 3FF Busy Bit Readable High Byte LOW Command N0/BUSCommand SET xyz 000 0 Noop no Operation Command Sequencing This register is updated upon an Allocate Memory MMU command Failed Allocated Packet NumberPage Page Data Register READ/WRITE Data High Data LOW Space BANK2 Offset Name Type SymbolThrough Ah Ercv EPH INT Rxovr Alloc TX INT RCV INT Empty Ercv INT Rxovr Empty TX INTPage INT LOW Multicast Table Byte High MDOE=0 MDOE=1 NXNDEIOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO Bit MDO High Byte LOW Byte Chip REV Chip ID Value Device High Byte LOW RCV Byte Discr Full Duplex Ethernet Support Theory of OperationMemory Architecture Behavior in Fdse Mode Main 802.3 section affected by Fdse is Typical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine CSMA/CD MMU RAM RX Intr TX Intr Assumes Auto Release Option Selected Txempty Intr Driver Send and Allocate Routines Memory Partitioning Interrupt Generation Internal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Wrattri Pcmcia Configuration Registers DescriptionSreset Ireq 8002h Ethernet Configuration and Status Register Ecsr IOIs8Page LevIREQ Enable Pcmcia functionality, this bit must be set IOIs8 Reserved Audio 8024h Pin Replacement Register PRR Current Value Value Written NEW Value Ringevent Ringenable 8028h Extended Status RegisterESR 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register A15 A14 A13 A12 A11 A10 8032h Modem I/O Size Register Arbiter Functional Description of the BlocksMemory Management Unit BUS Interface Wait State Policy DMA Block Packet Number Fifos DMA MMU Packet Number Flow and Relevant Registers Csma Block AUI Network Interface10BASE-T Physical Interface Transmit Functions Receive Functions Page Eeprom Word Board Setup Information ISA ModeEthernet Individual Address I/O Base Address Register Address Diagnostic LEDs Arbitration ConsiderationsPage 64 X 16 Serial Eeprom MAP for ISA Mode 103 Parameter Symbo MIN TYP MAX Units Comments Maximum Guaranteed RatingsOperational Description ID Type Buffers Input LeakageIP Type Buffers Type Buffer OD24 Type Buffer OD16 Type BufferOD162 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test Condition INTRO-INTR3 Parameter MIN TYP MAX UnitsCapacitive Load on Outputs Data Valid Timing DiagramsA50, nREG NCE1 NOE D150 30 max Max Min 108 109 Address/nREG Setup Time to NWE LowNWE High NCE1 Low to nWE High Setup O Read Timing Table on the following 110 Parameter Min Typ Max Units O Write Timing Table on the following 112 100 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 114 NINPAC 115 Consecutive Pcmcia Write Cycles 116 Pcmcia Attribute Memory READ/WRITE A15=0 117 Mringoutb 118 ISA Consecutive Read Cycles 119 ISA Consecutive Write Cycles 120 ISA Consecutive Read and Write Cycles 121 Data Register Special Read Access 122 Data Register Special Write Access 123 BIT Mode Register Cycles 124 ISA Register Access When Using Bale 125 External ROM Read Access Using Bale 126 Eeprom Read 127 Eeprom Write 128 Memory Read Timing 129 External Endec Interface Start of Transmit 130 Differential Output Signal Timing 10BASE-T and AUI 131 Recp Recn Tperxpn Tperxp Tperxn Recp Recn Transmit Timing END of Frame AUI and 10BASE-T 134 Collision Timing AUI 135 Vtqfp Package Outline 136Page Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516