SMC Networks SMC91C95

WAKE_UP - “Magic Packet” is received if

enabled

RX_OVRN INT - Set when the receiver overruns

due to a failed memory allocation. The RX_OVRN

bit of the EPHSR will also be set, but if a new

packet is received it will be cleared. The

RX_OVRN INT bit, however, latches the overrun

condition for the purpose of being polled or

generating an interrupt, and will only be cleared by

writing the acknowledge register with the

RX_OVRN INT bit set.

ALLOC INT - Set when an MMU request for TX

pages allocation is completed. This bit is the

complement of the FAILED bit in the

ALLOCATION RESULT register. The ALLOC INT

ENABLE bit should only be set following an

allocation command, and cleared upon servicing

the interrupt.

TX EMPTY INT - Set if the TX FIFO goes empty,

can be used to generate a single interrupt at the

end of a sequence of packets enqueued for

transmission. This bit latches the empty condition,

and the bit will stay set until it is specifically cleared

by writing the acknowledge register with the TX

EMPTY INT bit set. If a real time reading of the

FIFO empty is desired, the bit should be first

cleared and then read. The TX EMPTY INT

ENABLE should only be set after the following

steps:

a) a packet is enqueued for transmission

b) the previous empty condition is cleared

(acknowledged)

TX INT - Set when at least one packet

transmission was completed. The first packet

number to be serviced can be read from the FIFO

PORTS register. The TX INT bit is always the logic

complement of the TEMPTY bit in the FIFO

PORTS register. After servicing a packet number,

its TX INT interrupt is removed by writing the

Interrupt Acknowledge Register with the TX INT bit

set.

RCV INT - Set when a receive interrupt is

generated. The first packet number to be serviced

can be read from the FIFO PORTS register. The

RCV INT bit is always the logic complement of the

REMPTY bit in the FIFO PORTS register.

ERCV INT - Early receive interrupt. Set whenever

a receive packet is being received, and the number

of bytes received into memory exceeds the value

programmed as ERCV THRESHOLD (Bank 3,

Offset Ch). ERCV INT stays set until

acknowledged by writing the INTERRUPT

ACKNOWLEDGE REGISTER with the ERCV INT

bit set.

NOTE:If the driver uses AUTO RELEASE mode it

should enable TX EMPTY INT as well as TX INT.

TX EMPTY INT will be set when the complete

sequence of packets is transmitted. TX INT will be

set if the sequence stops due to a fatal error on

any of the packets in the sequence.

NOTE:For edge triggered systems, the Interrupt

Service Routine should clear the Interrupt Mask

interrupts after the interrupt source is serviced

(acknowledged).