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SMC Networks SMC91C95 manual BIT Mode Register Cycles, 124

Models: SMC91C95

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A0-15 (ISA)

AEN

nIOWR

t3

nIORD

Z

D0-7

VALID ADDRESS

t5

VALID DATA OUT

VALID ADDRESS

t3

t7

Z

VALID DATA IN

t8

	Parameter	min	typ	max	units

t3	Address, nSBHE, AEN Setup to Control Active	25			ns
t5	nIORD Low to Valid Data			40	ns
t7	Data Setup to nIOWR Rising	30			ns
t8	Data Hold after nIOWR Rising	9			ns

FIGURE 32 - 8-BIT MODE REGISTER CYCLES

A0-19

ADDRESS VALID

t3

t4

nMEMRD

Z

D0-15

	Parameter	min	typ	max	units

t3	Address Setup to Control Active	25			ns
t4	Address Hold after Control Inactive	20			ns
t16	nMEMRD Low to nROM Low	0		25	ns
t17	nMEMRD High to nROM High	0		30	ns

BALE tied high

FIGURE 33 - EXTERNAL ROM READ ACCESS

124

Image 124

SMC Networks SMC91C95 manual BIT Mode Register Cycles, 124

Contents

Features Bus InterfaceTable of Contents Network Interface PIN ConfigurationSoftware Drivers General Description OverviewPage ISA Uses non-volatile jumperless setup via serial EepromPcmcia Function ISA Pcmcia Number Pins PIN RequirementsCrystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GND Total PinsRecp ColnPIN no Name Symbol Type Description Description of PIN FunctionsISA Byte High Enable input. Asserted low Pcmcia Card Enable 2 input. Used toEnable Select card on odd byte accesses Ready ResetApplication of the VCC or Reset which ever ISA Output. Active high interrupt signal.Value of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when notWhenever the SMC91C95 is in 16 bit mode Enable Function bit in the EcorIs with Input. Active low read strobe used to access Interrupt pin if enabledPin is active high when either the Pwrdwn Output B Powerdown mode Pwrdwn bit is zeroValue of the Mringin input. When entering Pin when enabled by the Audio bit ModemEeprom Eesk Eeprom EecsEeprom Eedo Sdout EepromRxclk TXDRegister AUITPE Tpetxdp Tperxn TPE TpetxpTxclk Endec VSSAvss Buffer TypesSMC91C95 SMC91C95 SMC91C95 Internal Block Diagram BIT Mode Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15Functional Description Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15 Even byte IOis8=1 + nEN16=1.16BIT=0No Cycle Even byteSMC91C95 Address Spaces Signals ISA Pcmci ON-CHIP Depth Width UsedROM Buffer Memory Mapping and Paging VS. Receive and TX Area TX Completion CPU Side TX FifoFifo Receive Queue and Mapping Block Diagram SMC91C95Internal WithPacket Format in Buffer Memory Transmit Packet Receive PacketODD ODD CRCByte before the Control Byte should be ignored Receive Frame Status Word Address Hash Value Multicast Table BITFunction Pcmcia Mode ISA Mode Interrupt Output NIREQ when either function isInterrupt Structure SMC91C95 Interrupt MergingReset Logic Reset FunctionsEcor McorPowerdown Logic Powerdown FunctionsPowerdown Powers Does not Entered Exited Power Down PwrdwnPcmcia Configuration Registers Address 8000-803Eh Pcmcia Attribute Memory Address 0- 7FFEhAttribute Memory Address Using Serial Eeprom 7FFEh 8000h 803EhISA and Pcmcia Mode TypesymbolSpace OffsetnameInternal I/O Space Mapping BANK0 BANK1 BANK2 BANK3 BANK4 BANK5Bank Select Register Offset Name Type Symbol READ/WRITE BSR High Byte LOW BS2BS0 BS2 BS1 BS0 BANK#High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet LOW Pade Forco Loop Txena ByteTransmits AUI Fdse Fduplx Ephloop Loop Loops AT NetworkHigh Link CTR EXC Lost Latcol Wakeu Byte OvrnCarr LOW LTX Sqet LTX MULPage High Soft Strip Rxen Byte RST CARLOW Almul Prms Byte Abort Rxabort RxovrnintPage Memory Size Actual Memory Register FFHSpace BANK0 Offset Name Type Symbol Memory Configuration MCRRegister READ/WRITE DeviceHigh Full SET AUI Byte Wait Step SelecDIS INT ByteINT SEL1 INT SEL0 Interrupt PIN Used A15 A14 A13 Byte LOW ROM SizeRA17 RA15 RA14High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte High RCV Release LOW Eeprom Reload Store Byte EnableWakeu Auto Byte BAD Pcmcia Eeprom to Sram Memory Map 3FA 3FC3FD 3FFHigh Byte LOW Command N0/BUS Command SET xyzBusy Bit Readable 000 0 Noop no OperationCommand Sequencing This register is updated upon an Allocate Memory MMU command Failed Allocated Packet NumberPage Page Through Ah Space BANK2 Offset Name Type SymbolData Register READ/WRITE Data High Data LOW Ercv EPH INT Rxovr Alloc TX INT RCV INT Empty Ercv INT Rxovr Empty TX INTPage INT LOW Multicast Table Byte High NXNDE IOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDOMDOE=0 MDOE=1 Bit MDOHigh Byte LOW Byte Chip REV Chip ID Value DeviceHigh Byte LOW RCV Byte DiscrMemory Architecture Theory of OperationFull Duplex Ethernet Support Behavior in Fdse Mode Main 802.3 section affected by Fdse isTypical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine CSMA/CD MMU RAMRX Intr TX Intr Assumes Auto Release Option SelectedTxempty Intr Driver Send and Allocate Routines Memory Partitioning Interrupt GenerationInternal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Pcmcia Configuration Registers Description SresetWrattri Ireq8002h Ethernet Configuration and Status Register Ecsr IOIs8Page LevIREQ Enable Pcmcia functionality, this bit must be setIOIs8 Reserved Audio 8024h Pin Replacement Register PRR Current Value Value Written NEW ValueRingevent Ringenable 8028h Extended Status RegisterESR802Ah Modem I/O Base Register 802Ch Modem I/O Base Register A15 A14 A13 A12 A11 A108032h Modem I/O Size Register Memory Management Unit Functional Description of the BlocksArbiter BUS Interface Wait State PolicyDMA Block Packet Number Fifos DMA MMU Packet Number Flow and Relevant RegistersCsma Block Network Interface 10BASE-TAUI Physical InterfaceTransmit Functions Receive Functions Page Board Setup Information ISA Mode Ethernet Individual Address I/O Base AddressEeprom Word Register AddressDiagnostic LEDs Arbitration ConsiderationsPage 64 X 16 Serial Eeprom MAP for ISA Mode 103Operational Description Maximum Guaranteed RatingsParameter Symbo MIN TYP MAX Units Comments Input Leakage IP Type BuffersID Type Buffers Type BufferOD16 Type Buffer OD162 Type BufferOD24 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test ConditionCapacitive Load on Outputs Parameter MIN TYP MAX UnitsINTRO-INTR3 Timing Diagrams A50, nREG NCE1 NOE D150 30 max Max MinData Valid 108NWE High NCE1 Low to nWE High Setup Address/nREG Setup Time to NWE Low109 O Read Timing Table on the following 110Parameter Min Typ Max Units O Write Timing Table on the following 112100 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 114NINPAC 115Consecutive Pcmcia Write Cycles 116Pcmcia Attribute Memory READ/WRITE A15=0 117Mringoutb 118ISA Consecutive Read Cycles 119ISA Consecutive Write Cycles 120ISA Consecutive Read and Write Cycles 121Data Register Special Read Access 122Data Register Special Write Access 123BIT Mode Register Cycles 124ISA Register Access When Using Bale 125External ROM Read Access Using Bale 126Eeprom Read 127Eeprom Write 128Memory Read Timing 129External Endec Interface Start of Transmit 130Differential Output Signal Timing 10BASE-T and AUI 131Recp Recn TperxpnTperxp Tperxn Recp Recn Transmit Timing END of Frame AUI and 10BASE-T 134Collision Timing AUI 135Vtqfp Package Outline 136Page Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516