SMC Networks SMC91C95

I/O SPACE - BANK2

OFFSET NAME TYPE SYMBOL

0MMU COMMAND REGISTER WRITE ONLY

BUSY Bit Readable MMUCR

This register is used by the CPU to control the memory allocation, de-allocation, TX FIFO and RX FIFO

control. The three command bits determine the command issued as described below:

HIGH

BYTE

LOW

BYTE COMMAND 0 0 N2 N1 N0/BUS

xyz

COMMAND SET:

xyz

000 0) NOOP - NO OPERATION

001 1) ALLOCATE MEMORY FOR TX - N2,N1,N0 defines the amount of memory requested as

(value + 1) * 256 bytes. Namely N2,N1,N0 = 1 will request 2 * 256 = 512 bytes. Valid range for

N2,N1,N0 is 0 through 5. A shift-based divide by 256 of the packet length yields the

appropriate value to be used as N2,N1,N0. Immediately generates a completion code at the

ALLOCATION RESULT REGISTER. Can optionally generate an interrupt on successful

completion. The allocation time can take worst case (N2,N1,N0 + 2) * 200ns.

010 2) RESET MMU TO INITIAL STATE - Frees all memory allocations, clears relevant interrupts,

resets packet FIFO pointers.

011 3) REMOVE FRAME FROM TOP OF RX FIFO - To be issued after CPU has completed

processing of present receive frame. This command removes the receive packet number from

the RX FIFO and brings the next receive frame (if any) to the RX area (output of RX FIFO).

100 4) REMOVE AND RELEASE TOP OF RX FIFO - Like 3) but also releases all memory used by

the packet presently at the RX FIFO output.

101 5) RELEASE SPECIFIC PACKET - Frees all pages allocated to the packet specified in the

PACKET NUMBER REGISTER. Should not be used for frames pending transmission.

Typically used to remove transmitted frames, after reading their completion status. Can be

used following 3) to release receive packet memory in a more flexible way than 4).