Command Sequencing | SMC Networks SMC91C95 specification

1106) ENQUEUE PACKET NUMBER INTO TX FIFO - This is the normal method of transmitting a packet just loaded into RAM. The packet number to be enqueued is taken from the PACKET NUMBER REGISTER.

1117) RESET TX FIFOs - This command will reset both TX FIFOs: the TX FIFO holding the packet

numbers awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory.

NOTE 1: Only command 1) uses N2,N1,N0.

NOTE 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command.

NOTE 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet number has memory allocated to it.

COMMAND SEQUENCING

A second allocate command (command 1) should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt.

A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing

command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low.

BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command.

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SMC Networks SMC91C95 manual Command Sequencing

Contents

Bus Interface Features Table of Contents PIN Configuration Network InterfaceSoftware Drivers Overview General DescriptionPage Uses non-volatile jumperless setup via serial Eeprom ISAPcmcia PIN Requirements Function ISA Pcmcia Number Pins Total Pins Crystal OSC XTAL1 XTAL2 Power VDD Avdd Ground GNDRecp Coln Description of PIN Functions PIN no Name Symbol Type Description Pcmcia Card Enable 2 input. Used to ISA Byte High Enable input. Asserted lowEnable Select card on odd byte accesses Ready Reset ISA Output. Active high interrupt signal. Application of the VCC or Reset which everValue of INT SEL1-0 bits in the Configuration Register. This interrupt is tri-stated when not Enable Function bit in the Ecor Whenever the SMC91C95 is in 16 bit modeIs with Input. Active low read strobe used to access Interrupt pin if enabled Output B Powerdown mode Pwrdwn bit is zero Pin is active high when either the PwrdwnValue of the Mringin input. When entering Pin when enabled by the Audio bit Modem Eeprom Eecs Eeprom EeskEeprom Eedo Sdout Eeprom TXD RxclkRegister AUI Tperxn TPE Tpetxp TPE TpetxdpTxclk VSS EndecAvss Buffer Types SMC91C95 SMC91C95 SMC91C95 Internal Block Diagram Bus Transactions in ISA Mode NSBHE D0-D7 D8-D15 BIT ModeFunctional Description Even byte IOis8=1 + nEN16=1.16BIT=0 Bus Transactions in Pcmcia Mode NCE1 NCE2 D0-D7 D8-D15No Cycle Even byte Signals ISA Pcmci ON-CHIP Depth Width Used SMC91C95 Address SpacesROM Buffer Memory Mapping and Paging VS. Receive and TX Area CPU Side TX Fifo TX CompletionFifo Receive Queue and Mapping SMC91C95 Block DiagramInternal With Transmit Packet Receive Packet Packet Format in Buffer Memory ODD CRC ODDByte before the Control Byte should be ignored Address Hash Value Multicast Table BIT Receive Frame Status Word Interrupt Output NIREQ when either function is Function Pcmcia Mode ISA ModeInterrupt Structure SMC91C95 Interrupt Merging Reset Functions Reset LogicEcor Mcor Powerdown Functions Powerdown LogicPowerdown Powers Does not Entered Exited Power Down Pwrdwn Pcmcia Attribute Memory Address 0- 7FFEh Pcmcia Configuration Registers Address 8000-803Eh 7FFEh 8000h 803Eh Attribute Memory Address Using Serial Eeprom Typesymbol ISA and Pcmcia ModeSpace Offsetname BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 Internal I/O Space Mapping High Byte LOW BS2 Bank Select Register Offset Name Type Symbol READ/WRITE BSRBS0 BS2 BS1 BS0 BANK# LOW Pade Forco Loop Txena Byte High Fdse EPH STP Fdupl MON Nocrc Byte Loop Sqet AUI Fdse Fduplx Ephloop Loop Loops AT Network Transmits Ovrn High Link CTR EXC Lost Latcol Wakeu ByteCarr LOW LTX Sqet LTX MULPage Strip Rxen Byte RST CAR High SoftLOW Almul Prms Byte Abort Rxabort RxovrnintPage FFH Memory Size Actual Memory Register MCR Space BANK0 Offset Name Type Symbol Memory ConfigurationRegister READ/WRITE Device Selec High Full SET AUI Byte Wait StepDIS INT Byte INT SEL1 INT SEL0 Interrupt PIN Used Byte LOW ROM Size A15 A14 A13RA17 RA15 RA14 High Address Byte LOW High Byte LOW Byte High Data Byte LOW Data Byte Release LOW Eeprom Reload Store Byte Enable High RCVWakeu Auto Byte BAD Pcmcia Eeprom to Sram Memory Map 3FC 3FA3FD 3FF Command SET xyz High Byte LOW Command N0/BUSBusy Bit Readable 000 0 Noop no Operation Command Sequencing Failed Allocated Packet Number This register is updated upon an Allocate Memory MMU commandPage Page Space BANK2 Offset Name Type Symbol Through AhData Register READ/WRITE Data High Data LOW Ercv INT Rxovr Empty TX INT Ercv EPH INT Rxovr Alloc TX INT RCV INT EmptyPage INT LOW Multicast Table Byte High IOS2 IOS1 IOS0 Byte LOW Mdoe Mclk MDI MDO NXNDEMDOE=0 MDOE=1 Bit MDO Chip ID Value Device High Byte LOW Byte Chip REV Byte Discr High Byte LOW RCV Theory of Operation Memory ArchitectureFull Duplex Ethernet Support Main 802.3 section affected by Fdse is Behavior in Fdse Mode Typical Flow of Events for Transmit Driver CSMA/CD Side Typical Flow of Events for Receive Driver CSMA/CD Side Ethernet Interrupt Service Routine MMU RAM CSMA/CD RX Intr Assumes Auto Release Option Selected TX Intr Txempty Intr Driver Send and Allocate Routines Interrupt Generation Memory Partitioning Internal VS. External Attribute Memory MAP Attribute Memory Decodes Using Serial Eprom Sreset Pcmcia Configuration Registers DescriptionWrattri Ireq IOIs8 8002h Ethernet Configuration and Status Register EcsrPage Pcmcia functionality, this bit must be set LevIREQ Enable IOIs8 Reserved Audio Current Value Value Written NEW Value 8024h Pin Replacement Register PRR 8028h Extended Status RegisterESR Ringevent Ringenable A15 A14 A13 A12 A11 A10 802Ah Modem I/O Base Register 802Ch Modem I/O Base Register 8032h Modem I/O Size Register Functional Description of the Blocks Memory Management UnitArbiter Wait State Policy BUS Interface DMA Block Packet Number Fifos MMU Packet Number Flow and Relevant Registers DMA Csma Block 10BASE-T Network InterfaceAUI Physical Interface Transmit Functions Receive Functions Page Ethernet Individual Address I/O Base Address Board Setup Information ISA ModeEeprom Word Register Address Arbitration Considerations Diagnostic LEDsPage 103 64 X 16 Serial Eeprom MAP for ISA Mode Maximum Guaranteed Ratings Operational DescriptionParameter Symbo MIN TYP MAX Units Comments IP Type Buffers Input LeakageID Type Buffers Type Buffer OD162 Type Buffer OD16 Type BufferOD24 Type Buffer Limits Parameter Symbo MIN TYP MAX Unit Test Condition Parameter MIN TYP MAX Units Capacitive Load on OutputsINTRO-INTR3 A50, nREG NCE1 NOE D150 30 max Max Min Timing DiagramsData Valid 108 Address/nREG Setup Time to NWE Low NWE High NCE1 Low to nWE High Setup109 110 O Read Timing Table on the following Parameter Min Typ Max Units 112 O Write Timing Table on the following 100 114 Card Configuration Registers READ/WRITE Pcmcia Mode A15=1 115 NINPAC 116 Consecutive Pcmcia Write Cycles 117 Pcmcia Attribute Memory READ/WRITE A15=0 118 Mringoutb 119 ISA Consecutive Read Cycles 120 ISA Consecutive Write Cycles 121 ISA Consecutive Read and Write Cycles 122 Data Register Special Read Access 123 Data Register Special Write Access 124 BIT Mode Register Cycles 125 ISA Register Access When Using Bale 126 External ROM Read Access Using Bale 127 Eeprom Read 128 Eeprom Write 129 Memory Read Timing 130 External Endec Interface Start of Transmit 131 Differential Output Signal Timing 10BASE-T and AUI Tperxpn Recp Recn Tperxp Tperxn Recp Recn 134 Transmit Timing END of Frame AUI and 10BASE-T 135 Collision Timing AUI 136 Vtqfp Package OutlinePage Kennedy Drive Hauppauge, NY 516 435-6000 FAX 516