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SMC Networks SMC91C95 - page 27

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FIGURE 6 - RECEIVE QUEUE AND MAPPING

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Contents

Main SMC91C95 PRELIMINARY ISA/PCMCIA Full Duplex Single-Chip Ethernet and Modem Controller with RAM FEATURES TABLE OF CONTENTS Related Documentation PIN CONFIGURATION SMC91C95 128 Pin VTQFP GENERAL DESCRIPTION OVERVIEW Page Page PIN REQUIREMENTS Page Page Page Page Page Page Page Page Page Page Figure 1 - SMC91C95 System Block Diagram for ISA Bus with Boot PROM 10BASET AUI CABLE SIDE SMC91C95 DIAGNOSTIC BUFFER ADDRESS SYSTEM BUS SMC91C95 Figure 2 - SMC91C95 System Block Diagram for Dual Function PCMCIA Card Figure 3 - SMC91C95 Internal Block Diagram FUNCTIONAL DESCRIPTION Page Page Page FIGURE 4 - MAPPING AND PAGING VS. RECEIVE AND TX AREA FIGURE 5 - TRANSMIT QUEUES AND MAPPING B A B C TX FIFO C CPU SIDE TX COMPLETION FIFO Page FIGURE 7 - SMC91C95 INTERNAL BLOCK DIAGRAM WITH DATA PATH Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page Page FIGURE 9 - INTERRUPT STRUCTURE Page Page Page Page THEORY OF OPERATION Page Page Page FIGURE 10 - ETHERNET INTERRUPT SERVICE ROUTINE FIGURE 11 - INTERRUPT GENERATION FOR TRANSMIT, RECEIVE, MMU CSMA/CD MMU RAM FIGURE 12 - RX INTR FIGURE 13 - TX INTR (Assumes Auto Release Option Selected) FIGURE 14 - TXEMPTY INTR FIGURE 15 - DRIVER SEND AND ALLOCATE ROUTINES Page Page Page PCMCIA CONFIGURATION REGISTERS DESCRIPTION Page Page Page Page Page Page Page Page FUNCTIONAL DESCRIPTION OF THE BLOCKS Page Page Page FIGURE 16 - MMU PACKET NUMBER FLOW AND RELEVANT REGISTERS CSMA/CD MMU RAM DMA Page Page Page Page Page Page Page FIGURE 17 - 64 X 16 SERIAL EEPROM MAP FOR ISA MODE OPERATIONAL DESCRIPTION Page Page Page TIMING DIAGRAMS Page Page Page FIGURE 21 - (I/O WRITE TIMING) (Table on the following page) Page FIGURE 22 - CARD CONFIGURATION REGISTERS - READ/WRITE PCMCIA MODE (A15=1) FIGURE 23 - PCMCIA CONSECUTIVE READ CYCLES FIGURE 24 - CONSECUTIVE PCMCIA WRITE CYCLES FIGURE 25 - PCMCIA ATTRIBUTE MEMORY READ/WRITE (A15=0) Page FIGURE 27 - ISA CONSECUTIVE READ CYCLES FIGURE 28 - ISA CONSECUTIVE WRITE CYCLES FIGURE 29 - ISA CONSECUTIVE READ AND WRITE CYCLES FIGURE 30 - DATA REGISTER SPECIAL READ ACCESS FIGURE 31 - DATA REGISTER SPECIAL WRITE ACCESS FIGURE 32 - 8-BIT MODE REGISTER CYCLES FIGURE 33 - EXTERNAL ROM READ ACCESS FIGURE 34 - ISA REGISTER ACCESS WHEN USING BALE FIGURE 35 - EXTERNAL ROM READ ACCESS USING BALE FIGURE 36 - EEPROM READ FIGURE 37 - EEPROM WRITE FIGURE 38 - MEMORY READ TIMING FIGURE 39 - MEMORY WRITE TIMING FIGURE 40 - EXTERNAL ENDEC INTERFACE - START OF TRANSMIT FIGURE 41 - EXTERNAL ENDEC INTERFACE - RECEIVE DATA (RXD SAMPLED BY FALLING RXCLK) FIGURE 42 - DIFFERENTIAL OUTPUT SIGNAL TIMING (10BASE-T AND AUI) FIGURE 43 - RECEIVE TIMING - START OF FRAME (AUI AND 10BASE-T) FIGURE 44 - RECEIVE TIMING - END OF FRAME (AUI AND 10BASE-T) FIGURE 45 - TRANSMIT TIMING - END OF FRAME (AUI AND 10BASE-T) FIGURE 46 - COLLISION TIMING (AUI) 0 Hd D FIGURE 47 - VTQFP PACKAGE OUTLINE L c 0

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