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FIGURE 14 - TXEMPTY INTR
TXEMPTY INTR
Write Acknowledge Reg. with
TXEMPTY Bit Set
Read TXEMPTY & TX INTR
Acknowledge TXINTR
Re-Enable TXENA
Return to ISR
Issue "Release" Command
Restore Packet Number
TXEMPTY = 0
&
TXINT = 0
(Waiting for Completion)
TXEMPTY = X
&
TXINT = 1
(Transmission Failed)
TXEMPTY = 1
&
TXINT = 0
(Everything went through
successfully)
Read Pkt. # Register & Save
Write Address Pointer
Register
Read Status Word from RAM
Update Statistics
Update Variables