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The individual EMAC and MDIO signals for the MII interface are summarized in Table 1. For more information, refer to either the IEEE 802.3 standard or ISO/IEC
Figure 2. Ethernet Configuration—MII Connections
System
core
EMAC
MDIO
MII_TXCLK
MII_TXD[3−0]
MII_TXEN
MII_COL
MII_CRS
MII_RXCLK
MII_RXD[3−0]
MII_RXDV
MII_RXER
MDIO_CLK
MDIO_D
Physical layer device (PHY)
2.5MHz or
25 MHz
Transformer
RJ−45
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| Table 1. EMAC and MDIO Signals for MII Interface |
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| Signal | Type | Description |
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| MII_TXCLK | I | Transmit clock (MII_TXCLK). The transmit clock is a continuous clock that provides the timing |
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| reference for transmit operations. The MII_TXD and MII_TXEN signals are tied to this clock. The |
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| clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at 100 Mbps |
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| operation. |
| O | Transmit data (MII_TXD). The transmit data pins are a collection of 4 data signals comprising 4 bits | |
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| of data. MTDX0 is the |
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| valid only when MII_TXEN is asserted. |
| MII_TXEN | O | Transmit enable (MII_TXEN). The transmit enable signal indicates that the MII_TXD pins are |
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| generating nibble data for use by the PHY. It is driven synchronously to MII_TXCLK. |
| MII_COL | I | Collision detected (MII_COL). In |
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| when it detects a collision on the network. It remains asserted while the collision condition persists. |
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| This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK. |
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| In |
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| MII_COL pin will stop packet transmissions; packets in the process of being transmitted when |
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| MII_COL is asserted will complete transmission. The MII_COL pin should be held low if hardware |
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| transmit flow control is not used. |
| MII_CRS | I | Carrier sense (MII_CRS). In |
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| the network is not idle in either transmit or receive. The pin is deasserted when both transmit and |
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| receive are idle. This signal is not necessarily synchronous to MII_TXCLK nor MII_RXCLK. |
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| In |
| MII_RXCLK | I | Receive clock (MII_RXCLK). The receive clock is a continuous clock that provides the timing |
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| reference for receive operations. The MII_RXD, MII_RXDV, and MII_RXER signals are tied to this |
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| clock. The clock is generated by the PHY and is 2.5 MHz at 10 Mbps operation and 25 MHz at |
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| 100 Mbps operation. |
| I | Receive data (MII_RXD). The receive data pins are a collection of 4 data signals comprising 4 bits of | |
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| data. MRDX0 is the |
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| valid only when MII_RXDV is asserted. |
| MII_RXDV | I | Receive data valid (MII_RXDV). The receive data valid signal indicates that the MII_RXD pins are |
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| generating nibble data for use by the EMAC. It is driven synchronously to MII_RXCLK. |
| MII_RXER | I | Receive error (MII_RXER). The receive error signal is asserted for one or more MII_RXCLK periods |
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| to indicate that an error was detected in the received frame. This is meaningful only during data |
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| reception when MII_RXDV is active. |
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SPRUFL5B |
| EMAC/MDIO Module 15 | |
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