EMAC Module Registers | www.ti.com |
5.29 MAC Control Register (MACCONTROL)
The MAC control register (MACCONTROL) is shown in Figure 67 and described in Table 66.
Figure 67. MAC Control Register (MACCONTROL)
31 |
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| 16 |
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| Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
RMIISPEED
RXOFFLENBLOCK
RXOWNERSHIP
Rsvd
CMDIDLE
TXSHORTGAPEN
TXPTYPE
Reserved
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7 | 6 | 5 | 4 |
| 3 | 2 | 1 | 0 |
Reserved
TXPACE
GMIIEN
TXFLOWEN
RXBUFFERFLOWEN
Reserved
LOOPBACK
FULLDUPLEX
LEGEND: R/W = Read/Write; R = Read only;
Table 66. MAC Control Register (MACCONTROL) Field Descriptions
Bit |
| Field | Value | Description |
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| Reserved | 0 | Reserved | |
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15 |
| RMIISPEED |
| RMII interface transmit and receive speed select. |
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| 0 | Operate RMII interface in 10 Mbps speed mode. |
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| 1 | Operate RMII interface in 100 Mbps speed mode. |
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14 |
| RXOFFLENBLOCK |
| Receive offset / length word write block. |
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| 0 | Do not block the DMA writes to the receive buffer descriptor offset / buffer length word. |
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| 1 | Block all EMAC DMA controller writes to the receive buffer descriptor offset / buffer length |
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| words during packet processing. When this bit is set, the EMAC will never write the third word |
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| to any receive buffer descriptor. |
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13 |
| RXOWNERSHIP |
| Receive ownership write bit value. |
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| 0 | The EMAC writes the Receive ownership bit to 0 at the end of packet processing. |
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| 1 | The EMAC writes the Receive ownership bit to 1 at the end of packet processing. If you do not |
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| use the ownership mechanism, you can set this mode to preclude the necessity of software |
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| having to set this bit each time the buffer descriptor is used. |
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12 |
| Reserved | 0 | Reserved |
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11 |
| CMDIDLE |
| Command Idle bit |
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| 0 | Idle is not commanded. |
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| 1 | Idle is commanded (read IDLE in the MACSTATUS register). |
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10 |
| TXSHORTGAPEN |
| Transmit Short Gap Enable |
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| 0 | Transmit with a short IPG is disabled. Normal |
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| 1 | Transmit with a short IPG is enabled. Shorter |
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9 |
| TXPTYPE |
| Transmit queue priority type |
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| 0 | The queue uses a |
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| 1 | The queue uses a |
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| for transmission. |
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| Reserved | 0 | Reserved | |
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6 |
| TXPACE |
| Transmit pacing enable bit |
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| 0 | Transmit pacing is disabled. |
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| 1 | Transmit pacing is enabled. |
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5 |
| GMIIEN |
| GMII enable bit |
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| 0 | GMII RX and TX are held in reset. |
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| 1 | GMII RX and TX are enabled for receive and transmit. |
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110 | EMAC/MDIO Module |
| SPRUFL5B | |
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