MDIO Registers | www.ti.com |
4.14 MDIO User PHY Select Register 1 (USERPHYSEL1)
The MDIO user PHY select register 1 (USERPHYSEL1) is shown in Figure 38 and described in Table 36.
Figure 38. MDIO User PHY Select Register 1 (USERPHYSEL1)
31 |
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| 16 |
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| Reserved |
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15 | 8 | 7 | 6 | 5 | 4 | 0 |
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Reserved |
| LINKSEL | LINKINTENB | Rsvd |
| PHYADRMON |
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LEGEND: R/W = Read/Write; R = Read only;
Table 36. MDIO User PHY Select Register 1 (USERPHYSEL1) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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7 | LINKSEL |
| Link status determination select bit. Default value is 0, which implies that the link status is |
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| determined by the MDIO state machine. This is the only option supported on this device. |
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| 0 | The link status is determined by the MDIO state machine. |
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| 1 | Not supported. |
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6 | LINKINTENB |
| Link change interrupt enable. Set to 1 to enable link change status interrupts for the PHY address |
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| specified in PHYADRMON. Link change interrupts are disabled if this bit is cleared to 0. |
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| 0 | Link change interrupts are disabled. |
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| 1 | Link change status interrupts for PHY address specified in PHYADDRMON bits are enabled. |
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5 | Reserved | 0 | PHY address whose link status is to be monitored. |
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PHYADRMON | PHY address whose link status is to be monitored. | ||
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82 | EMAC/MDIO Module | SPRUFL5B |
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