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2.10 Packet Receive Operation
2.10.1Receive DMA Host Configuration
To configure the receive DMA for operation the host must:
•Initialize the receive addresses.
•Initialize the receive channel n DMA head descriptor pointer registers (RXnHDP) to 0.
•Write the MAC address hash n registers (MACHASH1 and MACHASH2), if multicast addressing is desired.
•If flow control is to be enabled, initialize:
–the receive channel n free buffer count registers (RXnFREEBUFFER)
–the receive channel n flow control threshold register (RXnFLOWTHRESH)
–the receive filter low priority frame threshold register (RXFILTERLOWTHRESH)
•Enable the desired receive interrupts using the receive interrupt mask set register (RXINTMASKSET) and the receive interrupt mask clear register (RXINTMASKCLEAR).
•Set the appropriate configuration bits in the MAC control register (MACCONTROL).
•Write the receive buffer offset register (RXBUFFEROFFSET) value (typically zero).
•Setup the receive channel(s) buffer descriptors and initialize RXnHDP.
•Enable the receive DMA controller by setting the RXEN bit in the receive control register (RXCONTROL).
•Configure and enable the receive operation, as desired, in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) and by using the receive unicast set register (RXUNICASTSET) and the receive unicast clear register (RXUNICASTCLEAR).
2.10.2Receive Channel Enabling
Each of the eight receive channels has an enable bit (RXCHnEN) in the receive unicast set register (RXUNICASTSET) that is controlled using RXUNICASTSET and the receive unicast clear register (RXUNICASTCLEAR). The RXCHnEN bits determine whether the given channel is enabled (when set to 1) to receive frames with a matching unicast or multicast destination address.
The RXBROADEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) determines if broadcast frames are enabled or filtered. If broadcast frames are enabled (when set to 1), then they are copied to only a single channel selected by the RXBROADCH bit in
RXMBPENABLE.
The RXMULTEN bit in RXMBPENABLE determines if hash matching multicast frames are enabled or filtered. Incoming multicast addresses (group addresses) are hashed into an index in the hash table. If the indexed bit is set then the frame hash matches and will be transferred to the channel selected by the RXMULTCH bit in RXMBPENABLE when multicast frames are enabled. The multicast hash bits are set in the MAC address hash n registers (MACHASH1 and MACHASH2).
The RXPROMCH bit in RXMBPENABLE selects the promiscuous channel to receive frames selected by the RXCMFEN, RXCSFEN, RXCEFEN, and RXCAFEN bits. These four bits allow reception of MAC control frames, short frames, error frames, and all frames (promiscuous), respectively.
2.10.3Receive Address Matching
All eight MAC addresses corresponding to the eight receive channels share the upper 40 bits. Only the lower byte is unique for each address. All eight receive addresses should be initialized, because pause frames are acted upon regardless of whether a channel is enabled or not.
A MAC address is written by first writing the address number (channel) to be written into the MAC index register (MACINDEX). The upper 32 bits of address are then written to the MAC address high bytes register (MACADDRHI), which is followed by writing the lower 16 bits of address to the MAC address low bytes register (MACADDRLO). Since all eight MAC addresses share the upper 40 bits of address, MACADDRHI needs to be written only the first time (for the first channel configured).
SPRUFL5B | EMAC/MDIO Module | 41 |
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