EMAC Control Module Registers | www.ti.com |
3.10EMAC Control Module Interrupt Core Transmit Interrupt Status Registers
The EMAC control module interrupt core
Figure 21. EMAC Control Module Interrupt Core 0-2 Transmit Interrupt Status Register (CnTXSTAT)
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| 16 |
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15 |
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| 8 |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
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TXCH7STAT | TXCH6STAT | TXCH5STAT | TXCH4STAT |
| TXCH3STAT | TXCH2STAT | TXCH1STAT | TXCH0STAT |
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LEGEND: R = Read only;
Table 18. EMAC Control Module Interrupt Core
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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7 | TXCH7STAT |
| Interrupt status for TX Channel 7 masked by the CnTXEN register |
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| 0 | TX Channel 7 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 7 satisfies conditions to generate a CnTXPULSE interrupt. |
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6 | TXCH6STAT |
| Interrupt status for TX Channel 6 masked by the CnTXEN register |
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| 0 | TX Channel 6 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 6 satisfies conditions to generate a CnTXPULSE interrupt. |
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5 | TXCH5STAT |
| Interrupt status for TX Channel 5 masked by the CnTXEN register |
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| 0 | TX Channel 5 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 5 satisfies conditions to generate a CnTXPULSE interrupt. |
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4 | TXCH4STAT |
| Interrupt status for TX Channel 4 masked by the CnTXEN register |
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| 0 | TX Channel 4 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 4 satisfies conditions to generate a CnTXPULSE interrupt. |
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3 | TXCH3STAT |
| Interrupt status for TX Channel 3 masked by the CnTXEN register |
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| 0 | TX Channel 3 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 3 satisfies conditions to generate a CnTXPULSE interrupt. |
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2 | TXCH2STAT |
| Interrupt status for TX Channel 2 masked by the CnTXEN register |
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| 0 | TX Channel 2 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 2 satisfies conditions to generate a CnTXPULSE interrupt. |
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1 | TXCH1STAT |
| Interrupt status for TX Channel 1 masked by the CnTXEN register |
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| 0 | TX Channel 1 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 1 satisfies conditions to generate a CnTXPULSE interrupt. |
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0 | TXCH0STAT |
| Interrupt status for TX Channel 0 masked by the CnTXEN register |
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| 0 | TX Channel 0 does not satisfy conditions to generate a CnTXPULSE interrupt. |
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| 1 | TX Channel 0 satisfies conditions to generate a CnTXPULSE interrupt. |
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66 | EMAC/MDIO Module | SPRUFL5B |
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