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5.48 Transmit Channel Completion Pointer Registers (TX0CP-TX7CP)
The transmit channel
Figure 86. Transmit Channel n Completion Pointer Register (TXnCP)
31 | 0 |
TXnCP
LEGEND: R/W = Read/Write;
Table 85. Transmit Channel n Completion Pointer Register (TXnCP) Field Descriptions
Bit | Field | Value | Description |
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TXnCP | Transmit channel n completion pointer register is written by the host with the buffer descriptor | ||
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| address for the last buffer processed by the host during interrupt processing. The EMAC uses the |
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| value written to determine if the interrupt should be deasserted. |
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5.49 Receive Channel Completion Pointer Registers (RX0CP-RX7CP)
The receive channel
Figure 87. Receive Channel n Completion Pointer Register (RXnCP)
31 | 0 |
RXnCP
LEGEND: R/W = Read/Write;
Table 86. Receive Channel n Completion Pointer Register (RXnCP) Field Descriptions
Bit | Field | Value | Description |
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RXnCP | Receive channel n completion pointer register is written by the host with the buffer descriptor | ||
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| address for the last buffer processed by the host during interrupt processing. The EMAC uses the |
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| value written to determine if the interrupt should be deasserted. |
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SPRUFL5B | EMAC/MDIO Module | 123 |
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