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4.9MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
The MDIO user command complete interrupt mask set register (USERINTMASKSET) is shown in Figure 33 and described in Table 31.
Figure 33. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
31 |
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| 16 |
| Reserved |
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15 | 2 | 1 | 0 |
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Reserved |
| USERACCESS1 | USERACCESS0 |
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LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect);
Table 31. MDIO User Command Complete Interrupt Mask Set Register (USERINTMASKSET)
Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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1 | USERACCESS1 |
| MDIO user interrupt mask set for USERINTMASKED[1]. Setting a bit to 1 will enable MDIO user |
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| command complete interrupts for the USERACCESS1 register. MDIO user interrupt for |
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| USERACCESS1 is disabled if the corresponding bit is 0. Writing a 0 to this bit has no effect. |
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| 0 | MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is |
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| disabled. |
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| 1 | MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is |
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| enabled. |
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0 | USERACCESS0 |
| MDIO user interrupt mask set for USERINTMASKED[0]. Setting a bit to 1 will enable MDIO user |
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| command complete interrupts for the USERACCESS0 register. MDIO user interrupt for |
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| USERACCESS0 is disabled if the corresponding bit is 0. Writing a 0 to this bit has no effect. |
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| 0 | MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is |
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| disabled. |
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| 1 | MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is |
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| enabled. |
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SPRUFL5B | EMAC/MDIO Module | 77 |
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