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5.19 MAC Interrupt Mask Set Register (MACINTMASKSET)
The MAC interrupt mask set register (MACINTMASKSET) is shown in Figure 57 and described in Table 56.
Figure 57. MAC Interrupt Mask Set Register (MACINTMASKSET)
31 |
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| 16 |
| Reserved |
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15 | 2 | 1 | 0 |
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Reserved |
| HOSTMASK | STATMASK |
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LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect);
Table 56. MAC Interrupt Mask Set Register (MACINTMASKSET) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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1 | HOSTMASK | Host error interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
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0 | STATMASK | Statistics interrupt mask set bit. Write 1 to enable interrupt, a write of 0 has no effect. | |
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5.20 MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
The MAC interrupt mask clear register (MACINTMASKCLEAR) is shown in Figure 58 and described in Table 57.
Figure 58. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR)
31 |
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| 16 |
| Reserved |
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15 | 2 | 1 | 0 |
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Reserved |
| HOSTMASK | STATMASK |
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LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect);
Table 57. MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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1 | HOSTMASK | Host error interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
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0 | STATMASK | Statistics interrupt mask clear bit. Write 1 to disable interrupt, a write of 0 has no effect. | |
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SPRUFL5B | EMAC/MDIO Module | 101 |
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