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3.11EMAC Control Module Interrupt Core Miscellaneous Interrupt Status Registers
The EMAC control module interrupt core
Figure 22. EMAC Control Module Interrupt Core 0-2 Miscellaneous Interrupt Status Register
(CnMISCSTAT)
31 |
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| 16 |
| Reserved |
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15 | 4 | 3 | 2 | 1 | 0 |
Reserved
STATPENDSTAT HOSTPENDSTAT
LINKINT0STAT
USERINT0STAT
LEGEND: R = Read only;
Table 19. EMAC Control Module Interrupt Core
(CnMISCSTAT)
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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3 | STATPENDSTAT |
| Interrupt status for EMAC STATPEND masked by the CnMISCEN register |
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| 0 | EMAC STATPEND does not satisfy conditions to generate a CnMISCPULSE interrupt. |
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| 1 | EMAC STATPEND satisfies conditions to generate a CnMISCPULSE interrupt. |
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2 | HOSTPENDSTAT |
| Interrupt status for EMAC HOSTPEND masked by the CnMISCEN register |
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| 0 | EMAC HOSTPEND does not satisfy conditions to generate a CnMISCPULSE interrupt. |
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| 1 | EMAC HOSTPEND satisfies conditions to generate a CnMISCPULSE interrupt. |
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1 | LINKINT0STAT |
| Interrupt status for MDIO LINKINT0 masked by the CnMISCEN register |
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| 0 | MDIO LINKINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt. |
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| 1 | MDIO LINKINT0 satisfies conditions to generate a CnMISCPULSE interrupt. |
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0 | USERINT0STAT |
| Interrupt status for MDIO USERINT0 masked by the CnMISCEN register |
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| 0 | MDIO USERINT0 does not satisfy conditions to generate a CnMISCPULSE interrupt. |
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| 1 | MDIO USERINT0 satisfies conditions to generate a CnMISCPULSE interrupt. |
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SPRUFL5B | EMAC/MDIO Module | 67 |
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