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4.7MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
The MDIO user command complete interrupt (unmasked) register (USERINTRAW) is shown in Figure 31 and described in Table 29.
Figure 31. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
31 |
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| 16 |
| Reserved |
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15 | 2 | 1 | 0 |
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Reserved |
| USERACCESS1 | USERACCESS0 |
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LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect);
Table 29. MDIO User Command Complete Interrupt (Unmasked) Register (USERINTRAW)
Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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1 | USERACCESS1 |
| MDIO User command complete event bit. When asserted, the bit indicates that the previously |
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| scheduled PHY read or write command using the USERACCESS1 register has completed. |
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| Writing a 1 will clear the event, writing a 0 has no effect. |
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| 0 | No MDIO user command complete event. |
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| 1 | The previously scheduled PHY read or write command using MDIO user access register |
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| USERACCESS1 has completed. |
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0 | USERACCESS0 |
| MDIO User command complete event bit. When asserted, the bit indicates that the previously |
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| scheduled PHY read or write command using the USERACCESS0 register has completed. |
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| Writing a 1 will clear the event, writing a 0 has no effect. |
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| 0 | No MDIO user command complete event. |
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| 1 | The previously scheduled PHY read or write command using MDIO user access register |
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| USERACCESS0 has completed. |
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SPRUFL5B | EMAC/MDIO Module | 75 |
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