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47 | Transmit Interrupt Mask Set Register (TXINTMASKSET) | 92 |
48 | Transmit Interrupt Mask Clear Register (TXINTMASKCLEAR) | 93 |
49 | MAC Input Vector Register (MACINVECTOR) | 94 |
50 | MAC End Of Interrupt Vector Register (MACEOIVECTOR) | 95 |
51 | Receive Interrupt Status (Unmasked) Register (RXINTSTATRAW) | 96 |
52 | Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) | 97 |
53 | Receive Interrupt Mask Set Register (RXINTMASKSET) | 98 |
54 | Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) | 99 |
55 | MAC Interrupt Status (Unmasked) Register (MACINTSTATRAW) | 100 |
56 | MAC Interrupt Status (Masked) Register (MACINTSTATMASKED) | 100 |
57 | MAC Interrupt Mask Set Register (MACINTMASKSET) | 101 |
58 | MAC Interrupt Mask Clear Register (MACINTMASKCLEAR) | 101 |
59 | Receive Multicast/Broadcast/Promiscuous Channel Enable Register (RXMBPENABLE) | 102 |
60 | Receive Unicast Enable Set Register (RXUNICASTSET) | 105 |
61 | Receive Unicast Clear Register (RXUNICASTCLEAR) | 106 |
62 | Receive Maximum Length Register (RXMAXLEN) | 107 |
63 | Receive Buffer Offset Register (RXBUFFEROFFSET) | 107 |
64 | Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH) | 108 |
65 | Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH) | 108 |
66 | Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) | 109 |
67 | MAC Control Register (MACCONTROL) | 110 |
68 | MAC Status Register (MACSTATUS) | 112 |
69 | Emulation Control Register (EMCONTROL) | 114 |
70 | FIFO Control Register (FIFOCONTROL) | 114 |
71 | MAC Configuration Register (MACCONFIG) | 115 |
72 | Soft Reset Register (SOFTRESET) | 115 |
73 | MAC Source Address Low Bytes Register (MACSRCADDRLO) | 116 |
74 | MAC Source Address High Bytes Register (MACSRCADDRHI) | 116 |
75 | MAC Hash Address Register 1 (MACHASH1) | 117 |
76 | MAC Hash Address Register 2 (MACHASH2) | 117 |
77 | Back Off Random Number Generator Test Register (BOFFTEST) | 118 |
78 | Transmit Pacing Algorithm Test Register (TPACETEST) | 118 |
79 | Receive Pause Timer Register (RXPAUSE) | 119 |
80 | Transmit Pause Timer Register (TXPAUSE) | 119 |
81 | MAC Address Low Bytes Register (MACADDRLO) | 120 |
82 | MAC Address High Bytes Register (MACADDRHI) | 121 |
83 | MAC Index Register (MACINDEX) | 121 |
84 | Transmit Channel n DMA Head Descriptor Pointer Register (TXnHDP) | 122 |
85 | Receive Channel n DMA Head Descriptor Pointer Register (RXnHDP) | 122 |
86 | Transmit Channel n Completion Pointer Register (TXnCP) | 123 |
87 | Receive Channel n Completion Pointer Register (RXnCP) | 123 |
88 | Statistics Register | 124 |
SPRUFL5B | List of Figures | 7 |
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