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4.10MDIO User Command Complete Interrupt Mask Clear Register
(USERINTMASKCLEAR)
The MDIO user command complete interrupt mask clear register (USERINTMASKCLEAR) is shown in Figure 34 and described in Table 32.
Figure 34. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
31 |
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| 16 |
| Reserved |
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| |
15 | 2 | 1 | 0 |
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Reserved |
| USERACCESS1 | USERACCESS0 |
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LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect);
Table 32. MDIO User Command Complete Interrupt Mask Clear Register (USERINTMASKCLEAR)
Field Descriptions
Bit | Field | Value | Description |
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|
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|
Reserved | 0 | Reserved | |
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1 | USERACCESS1 |
| MDIO user command complete interrupt mask clear for USERINTMASKED[1]. Setting the bit to |
|
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| 1 will disable further user command complete interrupts for USERACCESS1. Writing a 0 to this |
|
|
| bit has no effect. |
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| 0 | MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is |
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| enabled. |
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| 1 | MDIO user command complete interrupts for the MDIO user access register USERACCESS1 is |
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| disabled. |
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0 | USERACCESS0 |
| MDIO user command complete interrupt mask clear for USERINTMASKED[0]. Setting the bit to |
|
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| 1 will disable further user command complete interrupts for USERACCESS0. Writing a 0 to this |
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| bit has no effect. |
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| 0 | MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is |
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| enabled. |
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| 1 | MDIO user command complete interrupts for the MDIO user access register USERACCESS0 is |
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| disabled. |
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78 | EMAC/MDIO Module | SPRUFL5B |
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