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Texas Instruments TMS320C674X Receive Interrupt Mask Clear Register RXINTMASKCLEAR, Field, Value

Models: TMS320C674X

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5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

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EMAC Module Registers

5.16 Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

The receive interrupt mask clear register (RXINTMASKCLEAR) is shown in Figure 54 and described in Table 53.

Figure 54. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR)

31							16
			Reserved

			R-0
15	14	13	12	11	10	9	8

RX7THRESHMASK	RX6THRESHMASK	RX5THRESHMASK	RX4THRESHMASK	RX3THRESHMASK	RX2THRESHMASK	RX1THRESHMASK	RX0THRESHMASK

R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0
7	6	5	4	3	2	1	0

RX7MASK	RX6MASK	RX5MASK	RX4MASK	RX3MASK	RX2MASK	RX1MASK	RX0MASK
R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n= value after reset

Table 53. Receive Interrupt Mask Clear Register (RXINTMASKCLEAR) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	Reserved

15	RX7THRESHMASK	0-1	Receive channel 7 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

14	RX6THRESHMASK	0-1	Receive channel 6 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

13	RX5THRESHMASK	0-1	Receive channel 5 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

12	RX4THRESHMASK	0-1	Receive channel 4 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

11	RX3THRESHMASK	0-1	Receive channel 3 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

10	RX2THRESHMASK	0-1	Receive channel 2 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

9	RX1THRESHMASK	0-1	Receive channel 1 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

8	RX0THRESHMASK	0-1	Receive channel 0 threshold mask clear bit. Write 1 to disable interrupt; a write of 0 has no
			effect.

7	RX7MASK	0-1	Receive channel 7 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

6	RX6MASK	0-1	Receive channel 6 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

5	RX5MASK	0-1	Receive channel 5 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

4	RX4MASK	0-1	Receive channel 4 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

3	RX3MASK	0-1	Receive channel 3 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

2	RX2MASK	0-1	Receive channel 2 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

1	RX1MASK	0-1	Receive channel 1 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

0	RX0MASK	0-1	Receive channel 0 mask clear bit. Write 1 to disable interrupt; a write of 0 has no effect.

SPRUFL5B –April 2011	EMAC/MDIO Module	99
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Texas Instruments TMS320C674X Receive Interrupt Mask Clear Register RXINTMASKCLEAR, EMAC Module Registers, Field, Value

Contents

TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller EMAC Users GuideManagement Data Input/Output MDIO Module Submit Documentation Feedback SPRUFL5B -AprilPreface C0TXIMAX-C2TXIMAX Emulation Control Register EMCONTROL List of Figures Transmit Interrupt Mask Set Register TXINTMASKSET List of Tables List of TablesTransmit Interrupt Mask Set Register TXINTMASKSET Field Descriptions Notational Conventions Read This FirstPreface About This ManualRead This First Related Documentation From Texas Instruments1 Introduction EMAC/MDIO ModuleUsers Guide 1.2 FeaturesFigure 1. EMAC and MDIO Block Diagram 1.3 Functional Block Diagram2.1 Clock Control 2.3 Signal Descriptions1.4 Industry Standards Compliance Statement 2 ArchitectureType Figure 2. Ethernet Configuration-MII ConnectionsTable 1. EMAC and MDIO Signals for MII Interface Signal2.3.2 Reduced Media Independent Interface RMII Connections Table 1. EMAC and MDIO Signals for MII Interface continuedFigure 3. Ethernet Configuration-RMII Connections Table 2. EMAC and MDIO Signals for RMII InterfaceTable 3. Ethernet Frame Description 2.4 Ethernet Protocol Overview2.4.1 Ethernet Frame Format Figure 4. Ethernet Frame FormatFigure 5. Basic Descriptor Format 2.4.2 Ethernet’s Multiple Access Protocol2.5 Programming Interface 2.5.1 Packet Buffer DescriptorsTable 4. Basic Descriptor Description Figure 6. Typical Descriptor Linked ListWord Offset 2.5.2 Transmit and Receive Descriptor Queues 2.5.4 Transmit Buffer Descriptor Format 2.5.3 Transmit and Receive EMAC InterruptsBuffer Pointer Figure 7. Transmit Buffer Descriptor FormatExample 1. Transmit Buffer Descriptor in C Structure Format Next Descriptor Pointer2.5.4.4 Buffer Length 2.5.4.1 Next Descriptor Pointer2.5.4.2 Buffer Pointer 2.5.4.3 Buffer Offset2.5.4.10 Teardown Complete TDOWNCMPLT Flag 2.5.4.7 End of Packet EOP Flag2.5.4.8 Ownership OWNER Flag 2.5.4.9 End of Queue EOQ FlagFigure 8. Receive Buffer Descriptor Format 2.5.5 Receive Buffer Descriptor Format2.5.5.1 Next Descriptor Pointer 2.5.5.2 Buffer Pointer2.5.5.3 Buffer Offset Example 2. Receive Buffer Descriptor in C Structure Format2.5.5.7 End of Packet EOP Flag 2.5.5.4 Buffer Length2.5.5.5 Packet Length 2.5.5.6 Start of Packet SOP Flag2.5.5.11 Pass CRC PASSCRC Flag 2.5.5.18 Code Error CODEERROR Flag2.5.5.19 Alignment Error ALIGNERROR Flag 2.5.5.20 CRC Error CRCERROR Flag2.6.2 Bus Arbiter Figure 9. EMAC Control Module Block Diagram2.6 EMAC Control Module 2.6.1 Internal Memory2.7 MDIO Module 2.6.3 Interrupt Control2.7.1 MDIO Module Components 2.7.1.2 Global PHY Detection and Link State Monitoring Figure 10. MDIO Module Block Diagram2.7.1.4 PHY Register User Access 2.7.1.1 MDIO Clock Generator2.7.2 MDIO Module Operational Overview 2.7.2.1 Initializing the MDIO Module 2.7.2.2 Writing Data To a PHY Register2.7.2.3 Reading Data From a PHY Register #define PHYREGwriteregadr, phyadr, data 2.7.2.4 Example of MDIO Register Access CodeExample 3. MDIO Register Access Macros #define PHYREGreadregadr, phyadr2.8.1.1 Receive DMA Engine Figure 11. EMAC Module Block Diagram2.8 EMAC Module 2.8.1 EMAC Module Components2.8.1.6 MAC Transmitter 2.8.1.11 Clock and Reset Logic2.8.1.4 Transmit DMA Engine 2.8.1.5 Transmit FIFO2.9.1.2 Receive Inter-Frame Interval 2.9 MAC Interface2.9.1 Data Reception 2.9.1.1 Receive Control2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control 2.9.1.3.1 Collision-Based Receive Buffer Flow Control2.9.2.3 Adaptive Performance Optimization APO 2.9.2 Data Transmission2.9.2.1 Transmit Control 2.9.2.2 CRC Insertion2.9.2.7 Speed, Duplex, and Pause Frame Support 2.9.2.6 Transmit Flow Control2.10.3 Receive Address Matching 2.10.1 Receive DMA Host Configuration2.10 Packet Receive Operation 2.10.2 Receive Channel Enabling2.10.4 Hardware Receive QOS Support 2.10.5 Host Free Buffer Tracking2.10.6 Receive Channel Teardown 2.10.8 Promiscuous Receive Mode 2.10.7 Receive Frame ClassificationRXCMFEN Table 5. Receive Frame Treatment SummaryRXCAFEN RXCEFENTable 6. Middle of Frame Overrun Treatment 2.10.9 Receive Overrun2.11.1 Transmit DMA Host Configuration 2.11 Packet Transmit Operation2.11.2 Transmit Channel Teardown 2.13 Transfer Node Priority 2.12 Receive and Transmit Latency2.14 Reset Considerations 2.14.1 Software Reset Considerations2.14.2 Hardware Reset Considerations 2.15.3 MDIO Module Initialization 2.15 Initialization2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.2 EMAC Control Module Initialization2.15.4 EMAC Module Initialization 2.16.1.2 Receive Packet Completion Interrupts 2.16 Interrupt Support2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.1 Transmit Packet Completion Interrupts2.16.1.3 Statistics Interrupt 2.16.1.4 Host Error Interrupt2.16.1.5 Receive Threshold Interrupts 2.16.2 MDIO Module Interrupt Events and Requests2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt 2.16.3 Proper Interrupt Processing2.16.4 Interrupt Multiplexing 2.17 Power Management 2.18 Emulation ConsiderationsTable 7. Emulation Control Acronym 3 EMAC Control Module RegistersTable 8. EMAC Control Module Registers EMAC Control Module RegistersOffset 3.1 EMAC Control Module Revision ID Register REVIDTable 8. EMAC Control Module Registers continued Figure 12. EMAC Control Module Revision ID Register REVIDEMAC Control Module Registers 3.2 EMAC Control Module Software Reset Register SOFTRESETFigure 13. EMAC Control Module Software Reset Register SOFTRESET Table 10. EMAC Control Module Software Reset Register SOFTRESETField 3.3 EMAC Control Module Interrupt Control Register INTCONTROLFigure 14. EMAC Control Module Interrupt Control Register INTCONTROL Table 11. EMAC Control Module Interrupt Control Register INTCONTROLEMAC Control Module Registers C0RXTHRESHEN-C2RXTHRESHENCnRXTHRESHEN CnRXTHRESHENPage Page Value CnMISCENCnMISCEN FieldEMAC Control Module Registers C0RXTHRESHSTAT-C2RXTHRESHSTATCnRXTHRESHSTAT CnRXTHRESHSTATPage Page Value CnMISCSTATCnMISCSTAT FieldField CnRXIMAXCnRXIMAX EMAC Control Module RegistersValue CnTXIMAXCnTXIMAX FieldFigure 25. MDIO Revision ID Register REVID 4 MDIO Registers4.1 MDIO Revision ID Register REVID Table 22. Management Data Input/Output MDIO RegistersMDIO Registers 4.2 MDIO Control Register CONTROLFigure 26. MDIO Control Register CONTROL Table 24. MDIO Control Register CONTROL Field DescriptionsTable 25. PHY Acknowledge Status Register ALIVE Field Descriptions 4.3 PHY Acknowledge Status Register ALIVE4.4 PHY Link Status Register LINK Figure 27. PHY Acknowledge Status Register ALIVEField Descriptions 4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAWField Descriptions 4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKEDField Descriptions 4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAWField Descriptions Field Descriptions 4.10 MDIO User Command Complete Interrupt Mask Clear Register USERINTMASKCLEARField Descriptions MDIO Registers 4.11 MDIO User Access Register 0 USERACCESS0Figure 35. MDIO User Access Register 0 USERACCESS0 Table 33. MDIO User Access Register 0 USERACCESS0 Field DescriptionsField 4.12 MDIO User PHY Select Register 0 USERPHYSEL0Figure 36. MDIO User PHY Select Register 0 USERPHYSEL0 MDIO RegistersMDIO Registers 4.13 MDIO User Access Register 1 USERACCESS1Figure 37. MDIO User Access Register 1 USERACCESS1 Table 35. MDIO User Access Register 1 USERACCESS1 Field DescriptionsField 4.14 MDIO User PHY Select Register 1 USERPHYSEL1Figure 38. MDIO User PHY Select Register 1 USERPHYSEL1 MDIO RegistersAcronym Table 37. Ethernet Media Access Controller EMAC Registers5 EMAC Module Registers EMAC Module RegistersRegister Description Table 37. Ethernet Media Access Controller EMAC Registers continuedOffset AcronymRegister Description Table 37. Ethernet Media Access Controller EMAC Registers continuedOffset AcronymTable 38. Transmit Revision ID Register TXREVID Field Descriptions 5.1 Transmit Revision ID Register TXREVID5.2 Transmit Control Register TXCONTROL Figure 39. Transmit Revision ID Register TXREVIDEMAC Module Registers 5.3 Transmit Teardown Register TXTEARDOWNFigure 41. Transmit Teardown Register TXTEARDOWN Table 40. Transmit Teardown Register TXTEARDOWN Field DescriptionsTable 41. Receive Revision ID Register RXREVID Field Descriptions 5.4 Receive Revision ID Register RXREVID5.5 Receive Control Register RXCONTROL Figure 42. Receive Revision ID Register RXREVIDEMAC Module Registers 5.6 Receive Teardown Register RXTEARDOWNFigure 44. Receive Teardown Register RXTEARDOWN Table 43. Receive Teardown Register RXTEARDOWN Field DescriptionsField 5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAWFigure 45. Transmit Interrupt Status Unmasked Register TXINTSTATRAW EMAC Module RegistersField 5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKEDFigure 46. Transmit Interrupt Status Masked Register TXINTSTATMASKED EMAC Module RegistersField 5.9 Transmit Interrupt Mask Set Register TXINTMASKSETFigure 47. Transmit Interrupt Mask Set Register TXINTMASKSET EMAC Module RegistersField 5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEARFigure 48. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR EMAC Module RegistersEMAC Module Registers 5.11 MAC Input Vector Register MACINVECTORFigure 49. MAC Input Vector Register MACINVECTOR Table 48. MAC Input Vector Register MACINVECTOR Field DescriptionsField 5.12 MAC End Of Interrupt Vector Register MACEOIVECTORFigure 50. MAC End Of Interrupt Vector Register MACEOIVECTOR EMAC Module RegistersField 5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAWFigure 51. Receive Interrupt Status Unmasked Register RXINTSTATRAW EMAC Module RegistersField 5.14 Receive Interrupt Status Masked Register RXINTSTATMASKEDFigure 52. Receive Interrupt Status Masked Register RXINTSTATMASKED EMAC Module RegistersField 5.15 Receive Interrupt Mask Set Register RXINTMASKSETFigure 53. Receive Interrupt Mask Set Register RXINTMASKSET EMAC Module RegistersField 5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEARFigure 54. Receive Interrupt Mask Clear Register RXINTMASKCLEAR EMAC Module RegistersFigure 56. MAC Interrupt Status Masked Register MACINTSTATMASKED 5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED Figure 55. MAC Interrupt Status Unmasked Register MACINTSTATRAWFigure 58. MAC Interrupt Mask Clear Register MACINTMASKCLEAR 5.19 MAC Interrupt Mask Set Register MACINTMASKSET5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR Figure 57. MAC Interrupt Mask Set Register MACINTMASKSET5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register RXMBPENABLEField Descriptions Description Field Descriptions continuedField ValueDescription Field Descriptions continuedField ValueField 5.22 Receive Unicast Enable Set Register RXUNICASTSETFigure 60. Receive Unicast Enable Set Register RXUNICASTSET EMAC Module RegistersField 5.23 Receive Unicast Clear Register RXUNICASTCLEARFigure 61. Receive Unicast Clear Register RXUNICASTCLEAR EMAC Module RegistersTable 61. Receive Maximum Length Register RXMAXLEN Field Descriptions 5.24 Receive Maximum Length Register RXMAXLEN5.25 Receive Buffer Offset Register RXBUFFEROFFSET Figure 62. Receive Maximum Length Register RXMAXLENField Descriptions 5.27 Receive Channel Flow Control Threshold RegistersRX0FLOWTHRESH-RX7FLOWTHRESH Field DescriptionsDescription Figure 66. Receive Channel n Free Buffer Count Register RXnFREEBUFFEREMAC Module Registers FieldEMAC Module Registers 5.29 MAC Control Register MACCONTROLFigure 67. MAC Control Register MACCONTROL Table 66. MAC Control Register MACCONTROL Field DescriptionsSubmit Documentation Feedback FieldValue DescriptionEMAC Module Registers 5.30 MAC Status Register MACSTATUSFigure 68. MAC Status Register MACSTATUS Table 67. MAC Status Register MACSTATUS Field DescriptionsDescription Table 67. MAC Status Register MACSTATUS Field Descriptions continuedField ValueTable 68. Emulation Control Register EMCONTROL Field Descriptions 5.31 Emulation Control Register EMCONTROL5.32 FIFO Control Register FIFOCONTROL Figure 69. Emulation Control Register EMCONTROLTable 70. MAC Configuration Register MACCONFIG Field Descriptions 5.33 MAC Configuration Register MACCONFIG5.34 Soft Reset Register SOFTRESET Figure 71. MAC Configuration Register MACCONFIGFigure 74. MAC Source Address High Bytes Register MACSRCADDRHI 5.35 MAC Source Address Low Bytes Register MACSRCADDRLO5.36 MAC Source Address High Bytes Register MACSRCADDRHI Figure 73. MAC Source Address Low Bytes Register MACSRCADDRLOTable 74. MAC Hash Address Register 1 MACHASH1 Field Descriptions 5.37 MAC Hash Address Register 1 MACHASH15.38 MAC Hash Address Register 2 MACHASH2 Figure 75. MAC Hash Address Register 1 MACHASH1Table 76. Back Off Test Register BOFFTEST Field Descriptions 5.39 Back Off Test Register BOFFTEST5.40 Transmit Pacing Algorithm Test Register TPACETEST Figure 77. Back Off Random Number Generator Test Register BOFFTESTTable 78. Receive Pause Timer Register RXPAUSE Field Descriptions 5.41 Receive Pause Timer Register RXPAUSE5.42 Transmit Pause Timer Register TXPAUSE Figure 79. Receive Pause Timer Register RXPAUSEEMAC Module Registers 5.43 MAC Address Low Bytes Register MACADDRLOFigure 81. MAC Address Low Bytes Register MACADDRLO Table 80. MAC Address Low Bytes Register MACADDRLO Field DescriptionsFigure 83. MAC Index Register MACINDEX 5.44 MAC Address High Bytes Register MACADDRHI5.45 MAC Index Register MACINDEX Figure 82. MAC Address High Bytes Register MACADDRHI5.46 Transmit Channel DMA Head Descriptor Pointer Registers TX0HDP-TX7HDP Figure 87. Receive Channel n Completion Pointer Register RXnCP 5.48 Transmit Channel Completion Pointer Registers TX0CP-TX7CP5.49 Receive Channel Completion Pointer Registers RX0CP-RX7CP Figure 86. Transmit Channel n Completion Pointer Register TXnCP5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES 5.50 Network Statistics RegistersFigure 88. Statistics Register 5.50.1 Good Receive Frames Register RXGOODFRAMES5.50.5 Receive CRC Errors Register RXCRCERRORS 5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.10 Receive Frame Fragments Register RXFRAGMENTS 5.50.7 Receive Oversized Frames Register RXOVERSIZED5.50.8 Receive Jabber Frames Register RXJABBER 5.50.9 Receive Undersized Frames Register RXUNDERSIZED5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED 5.50.13 Receive Octet Frames Register RXOCTETS5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.18 Deferred Transmit Frames Register TXDEFERRED 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES 5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL 5.50.24 Transmit Underrun Error Register TXUNDERRUN5.50.20 Transmit Single Collision Frames Register TXSINGLECOLL 5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE 5.50.26 Transmit Octet Frames Register TXOCTETS5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64 5.50.33 Network Octet Frames Register NETOCTETS 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS Appendix A Glossary Table 87. Physical Layer Definitions Submit Documentation Feedback Appendix B Revision HistoryTable 88. Document Revision History Reference Additions/Modifications/DeletionsTI E2E Community Home Page IMPORTANT NOTICEProducts Applications