Rxfilterthresh | Texas Instruments TMS320C674X specs

EMAC Module Registers

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5.26 Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

The receive filter low priority frame threshold register (RXFILTERLOWTHRESH) is shown in Figure 64 and described in Table 63.

Figure 64. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

31				16
	Reserved

		R-0
15	8	7		0

Reserved				RXFILTERTHRESH

R-0				R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 63. Receive Filter Low Priority Frame Threshold Register (RXFILTERLOWTHRESH)

Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	RXFILTERTHRESH	0-FFh	Receive filter low threshold. These bits contain the free buffer count threshold value for filtering
			low priority incoming frames. This field should remain 0, if no filtering is desired.

5.27Receive Channel Flow Control Threshold Registers

(RX0FLOWTHRESH-RX7FLOWTHRESH)

The receive channel 0-7 flow control threshold register (RXnFLOWTHRESH) is shown in Figure 65 and described in Table 64.

Figure 65. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)

31				16
	Reserved
		R-0
15	8	7		0

Reserved				RXnFLOWTHRESH

R-0				R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 64. Receive Channel n Flow Control Threshold Register (RXnFLOWTHRESH)

Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7-0	RXnFLOWTHRESH	0-FFh	Receive flow threshold. These bits contain the threshold value for issuing flow control on
			incoming frames for channel n (when enabled).

108	EMAC/MDIO Module	SPRUFL5B –April 2011
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Texas Instruments TMS320C674X manual Receive Channel Flow Control Threshold Registers, Rxfilterthresh

Contents

Users Guide Submit Documentation Feedback C0MISCEN-C2MISCEN C0TXIMAX-C2TXIMAX Appendix a Appendix B List of Figures MAC Interrupt Mask Clear Register Macintmaskclear List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Signal Descriptions Industry Standards Compliance StatementClock Control Memory Map Emac and Mdio Signals for MII Interface Signal Type Description Emac and Mdio Signals for Rmii Interface Reduced Media Independent Interface Rmii Connections Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Word Basic Descriptor Description Field Field Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Next Descriptor Pointer Buffer PointerBuffer Offset Buffer Length End of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber Flag Emac Control Module Internal MemoryBus Arbiter CPU Mdio Module Interrupt ControlMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Mdio Module Operational Overview Initializing the Mdio Module Writing Data To a PHY RegisterReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Emac Module Emac Module ComponentsReceive DMA Engine Receive Fifo Clock and Reset Logic Transmit DMA EngineTransmit Fifo MAC Transmitter MAC Interface Data ReceptionReceive Control Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Transmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Hardware Receive QOS Support Host Free Buffer TrackingReceive Channel Teardown Promiscuous Receive Mode Receive Frame Classification Receive Frame Treatment Summary Receive Frame Treatment Receive Overrun Middle of Frame Overrun TreatmentMiddle of Frame Overrun Treatment Transmit DMA Host Configuration Packet Transmit OperationTransmit Channel Teardown Receive and Transmit Latency Transfer Node Priority Reset Considerations Software Reset ConsiderationsHardware Reset Considerations Initialization Enabling the EMAC/MDIO PeripheralEmac Control Module Initialization Mdio Module Initialization Emac Module Initialization Macintmaskset Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt Receive Threshold Interrupts Mdio Module Interrupt Events and RequestsLink Change Interrupt User Access Completion Interrupt Proper Interrupt ProcessingInterrupt Multiplexing Power Management Emulation ConsiderationsEmulation Control Emac Control Module Registers Acronym Register Description Emac Control Module Revision ID Register Revid Offset Acronym Register DescriptionBit Field Value Description Emac Control Module Software Reset Register Softreset Reset Emac Control Module Interrupt Control Register Intcontrol IntprescaleC2TXPACEEN Bit Field RXCH7EN TXCH7EN Statpenden Hostpenden LINKINT0EN USERINT0EN Statpenden RXCH7THRESHSTAT RXCH6THRESHSTATRXCH5THRESHSTAT RXCH4THRESHSTAT RXCH7STAT TXCH7STAT Statpendstat HostpendstatLINKINT0STAT USERINT0STAT Rximax Allowemacinterrupts Tximax Mdio Revision ID Register Revid Management Data Input/Output Mdio RegistersMdio Revision ID Register Revid Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions USERPHY1 USERPHY0 USERPHY1 Writing a 0 has no effect USERACCESS1 USERACCESS0 Effect W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Macconfig MacstatusEmcontrol Fifocontrol Network Statistics Registers Transmit Revision ID Register Txrevid Transmit Control Register TxcontrolTransmit Revision ID Register Txrevid Field Descriptions Transmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Transmit Teardown Register Txteardown Field DescriptionsTxtdnch Receive Revision ID Register Rxrevid Receive Control Register RxcontrolReceive Revision ID Register Rxrevid Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Receive Teardown Register Rxteardown Field DescriptionsRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsStatpend RX0THRESHPEND MAC End Of Interrupt Vector Register Maceoivector Intvect Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Unmasked Register Macintstatraw MAC Interrupt Status Masked Register MacintstatmaskedHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask Hostmask Rxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Receive Buffer Offset Register RxbufferoffsetReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Channel Flow Control Threshold Registers Rxfilterthresh Receive Channel n Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Txflowen RxbufferflowenLoopback Fullduplex MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions Rxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Back Off Test Register Bofftest Transmit Pacing Algorithm Test Register TpacetestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 Valid MAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Transmit Channel Completion Pointer Registers TX0CP-TX7CP Receive Channel Completion Pointer Registers RX0CP-RX7CP Network Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive CRC Errors Register Rxcrcerrors Receive Alignment/Code Errors Register RxaligncodeerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive QOS Filtered Frames Register Rxqosfiltered Receive Octet Frames Register RxoctetsGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Carrier Sense Errors Register Txcarriersense Transmit Octet Frames Register TxoctetsTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Physical Layer Definitions Term Definition Document Revision History Reference Additions/Modifications/Deletions Products Applications DSPRfid TI E2E Community Home