EMAC Control Module Registers | www.ti.com |
3.8EMAC Control Module Interrupt Core Receive Threshold Interrupt Status Registers
(C0RXTHRESHSTAT-C2RXTHRESHSTAT)
The EMAC control module interrupt core
Figure 19. EMAC Control Module Interrupt Core
(CnRXTHRESHSTAT)
31 |
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| Reserved |
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15 |
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| 8 |
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| Reserved |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RXCH7THRESH | RXCH6THRESH | RXCH5THRESH | RXCH4THRESH | RXCH3THRESH | RXCH2THRESH | RXCH1THRESH | RXCH0THRESH |
STAT | STAT | STAT | STAT | STAT | STAT | STAT | STAT |
LEGEND: R = Read only;
Table 16. EMAC Control Module Interrupt Core
(CnRXTHRESHSTAT)
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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7 | RXCH7THRESHSTAT |
| Interrupt status for RX Channel 7 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 7 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 7 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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6 | RXCH6THRESHSTAT |
| Interrupt status for RX Channel 6 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 6 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 6 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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5 | RXCH5THRESHSTAT |
| Interrupt status for RX Channel 5 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 5 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 5 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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4 | RXCH4THRESHSTAT |
| Interrupt status for RX Channel 4 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 4 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 4 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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3 | RXCH3THRESHSTAT |
| Interrupt status for RX Channel 3 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 3 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 3 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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2 | RXCH2THRESHSTAT |
| Interrupt status for RX Channel 2 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 2 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 2 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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1 | RXCH1THRESHSTAT |
| Interrupt status for RX Channel 1 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 1 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 1 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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0 | RXCH0THRESHSTAT |
| Interrupt status for RX Channel 0 masked by the CnRXTHRESHEN register |
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| 0 | RX Channel 0 does not satisfy conditions to generate a CnRXTHRESHPULSE interrupt. |
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| 1 | RX Channel 0 satisfies conditions to generate a CnRXTHRESHPULSE interrupt. |
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64 | EMAC/MDIO Module | SPRUFL5B |
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