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Texas Instruments TMS320C674X MAC Status Register MACSTATUS, EMAC Module Registers, Field, Value

Models: TMS320C674X

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5.30 MAC Status Register (MACSTATUS)

EMAC Module Registers

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5.30 MAC Status Register (MACSTATUS)

The MAC status register (MACSTATUS) is shown in Figure 68 and described in Table 67.

Figure 68. MAC Status Register (MACSTATUS)

31	30		24	23	20		19	18		16
IDLE		Reserved			TXERRCODE		Rsvd			TXERRCH

R-0		R-0			R-0		R-0				R-0
	15		12	11	10					8

		RXERRCODE		Reserved			RXERRCH

		R-0		R-0				R-0
	7			3	2			1		0

		Reserved				RXQOSACT	RXFLOWACT				TXFLOWACT
		R-0				R-0		R-0			R-0

LEGEND: R = Read only; -n= value after reset

Table 67. MAC Status Register (MACSTATUS) Field Descriptions

Bit	Field	Value	Description

31	IDLE		EMAC idle bit. This bit is cleared to 0 at reset; one clock after reset, it goes to 1.
		0	The EMAC is not idle.
		1	The EMAC is in the idle state.

30-24	Reserved	0	Reserved

23-20	TXERRCODE	0-Fh	Transmit host error code. These bits indicate that EMAC detected transmit DMA related host errors.
			The host should read this field after a host error interrupt (HOSTPEND) to determine the error. Host
			error interrupts require hardware reset in order to recover. A 0 packet length is an error, but it is not
			detected.
		0	No error
		1h	SOP error; the buffer is the first buffer in a packet, but the SOP bit is not set in software.
		2h	Ownership bit not set in SOP buffer
		3h	Zero next buffer descriptor pointer without EOP
		4h	Zero buffer pointer
		5h	Zero buffer length
		6h	Packet length error (sum of buffers is less than packet length)
		7h-Fh	Reserved

19	Reserved	0	Reserved

18-16	TXERRCH	0-7h	Transmit host error channel. These bits indicate which transmit channel the host error occurred on.
			This field is cleared to 0 on a host read.
		0	The host error occurred on transmit channel 0
		1h	The host error occurred on transmit channel 1
		2h	The host error occurred on transmit channel 2
		3h	The host error occurred on transmit channel 3
		4h	The host error occurred on transmit channel 4
		5h	The host error occurred on transmit channel 5
		6h	The host error occurred on transmit channel 6
		7h	The host error occurred on transmit channel 7

112	EMAC/MDIO Module	SPRUFL5B –April 2011
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Texas Instruments TMS320C674X manual MAC Status Register MACSTATUS Field Descriptions, EMAC Module Registers, Value

Contents

Users Guide TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller EMACManagement Data Input/Output MDIO Module SPRUFL5B -April Submit Documentation FeedbackPreface C0TXIMAX-C2TXIMAX Emulation Control Register EMCONTROL List of Figures Transmit Interrupt Mask Set Register TXINTMASKSET List of Tables List of TablesTransmit Interrupt Mask Set Register TXINTMASKSET Field Descriptions Read This First PrefaceAbout This Manual Notational ConventionsRelated Documentation From Texas Instruments Read This FirstEMAC/MDIO Module Users Guide1.2 Features 1 Introduction1.3 Functional Block Diagram Figure 1. EMAC and MDIO Block Diagram2.3 Signal Descriptions 1.4 Industry Standards Compliance Statement2 Architecture 2.1 Clock ControlFigure 2. Ethernet Configuration-MII Connections Table 1. EMAC and MDIO Signals for MII InterfaceSignal TypeTable 1. EMAC and MDIO Signals for MII Interface continued Figure 3. Ethernet Configuration-RMII ConnectionsTable 2. EMAC and MDIO Signals for RMII Interface 2.3.2 Reduced Media Independent Interface RMII Connections2.4 Ethernet Protocol Overview 2.4.1 Ethernet Frame FormatFigure 4. Ethernet Frame Format Table 3. Ethernet Frame Description2.4.2 Ethernet’s Multiple Access Protocol 2.5 Programming Interface2.5.1 Packet Buffer Descriptors Figure 5. Basic Descriptor FormatFigure 6. Typical Descriptor Linked List Table 4. Basic Descriptor DescriptionWord Offset 2.5.2 Transmit and Receive Descriptor Queues 2.5.3 Transmit and Receive EMAC Interrupts 2.5.4 Transmit Buffer Descriptor FormatFigure 7. Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure FormatNext Descriptor Pointer Buffer Pointer2.5.4.1 Next Descriptor Pointer 2.5.4.2 Buffer Pointer2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length2.5.4.7 End of Packet EOP Flag 2.5.4.8 Ownership OWNER Flag2.5.4.9 End of Queue EOQ Flag 2.5.4.10 Teardown Complete TDOWNCMPLT Flag2.5.5 Receive Buffer Descriptor Format 2.5.5.1 Next Descriptor Pointer2.5.5.2 Buffer Pointer Figure 8. Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format 2.5.5.3 Buffer Offset2.5.5.4 Buffer Length 2.5.5.5 Packet Length2.5.5.6 Start of Packet SOP Flag 2.5.5.7 End of Packet EOP Flag2.5.5.18 Code Error CODEERROR Flag 2.5.5.19 Alignment Error ALIGNERROR Flag2.5.5.20 CRC Error CRCERROR Flag 2.5.5.11 Pass CRC PASSCRC FlagFigure 9. EMAC Control Module Block Diagram 2.6 EMAC Control Module2.6.1 Internal Memory 2.6.2 Bus Arbiter2.6.3 Interrupt Control 2.7 MDIO Module2.7.1 MDIO Module Components Figure 10. MDIO Module Block Diagram 2.7.1.4 PHY Register User Access2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring2.7.2 MDIO Module Operational Overview 2.7.2.2 Writing Data To a PHY Register 2.7.2.1 Initializing the MDIO Module2.7.2.3 Reading Data From a PHY Register 2.7.2.4 Example of MDIO Register Access Code Example 3. MDIO Register Access Macros#define PHYREGreadregadr, phyadr #define PHYREGwriteregadr, phyadr, dataFigure 11. EMAC Module Block Diagram 2.8 EMAC Module2.8.1 EMAC Module Components 2.8.1.1 Receive DMA Engine2.8.1.11 Clock and Reset Logic 2.8.1.4 Transmit DMA Engine2.8.1.5 Transmit FIFO 2.8.1.6 MAC Transmitter2.9 MAC Interface 2.9.1 Data Reception2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval2.9.1.3.1 Collision-Based Receive Buffer Flow Control 2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control2.9.2 Data Transmission 2.9.2.1 Transmit Control2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization APO2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support2.10.1 Receive DMA Host Configuration 2.10 Packet Receive Operation2.10.2 Receive Channel Enabling 2.10.3 Receive Address Matching2.10.5 Host Free Buffer Tracking 2.10.4 Hardware Receive QOS Support2.10.6 Receive Channel Teardown 2.10.7 Receive Frame Classification 2.10.8 Promiscuous Receive ModeTable 5. Receive Frame Treatment Summary RXCAFENRXCEFEN RXCMFEN2.10.9 Receive Overrun Table 6. Middle of Frame Overrun Treatment2.11 Packet Transmit Operation 2.11.1 Transmit DMA Host Configuration2.11.2 Transmit Channel Teardown 2.12 Receive and Transmit Latency 2.13 Transfer Node Priority2.14.1 Software Reset Considerations 2.14 Reset Considerations2.14.2 Hardware Reset Considerations 2.15 Initialization 2.15.1 Enabling the EMAC/MDIO Peripheral2.15.2 EMAC Control Module Initialization 2.15.3 MDIO Module Initialization2.15.4 EMAC Module Initialization 2.16 Interrupt Support 2.16.1 EMAC Module Interrupt Events and Requests2.16.1.1 Transmit Packet Completion Interrupts 2.16.1.2 Receive Packet Completion Interrupts2.16.1.4 Host Error Interrupt 2.16.1.3 Statistics Interrupt2.16.2 MDIO Module Interrupt Events and Requests 2.16.1.5 Receive Threshold Interrupts2.16.2.1 Link Change Interrupt 2.16.3 Proper Interrupt Processing 2.16.2.2 User Access Completion Interrupt2.16.4 Interrupt Multiplexing 2.18 Emulation Considerations 2.17 Power ManagementTable 7. Emulation Control 3 EMAC Control Module Registers Table 8. EMAC Control Module RegistersEMAC Control Module Registers Acronym3.1 EMAC Control Module Revision ID Register REVID Table 8. EMAC Control Module Registers continuedFigure 12. EMAC Control Module Revision ID Register REVID Offset3.2 EMAC Control Module Software Reset Register SOFTRESET Figure 13. EMAC Control Module Software Reset Register SOFTRESETTable 10. EMAC Control Module Software Reset Register SOFTRESET EMAC Control Module Registers3.3 EMAC Control Module Interrupt Control Register INTCONTROL Figure 14. EMAC Control Module Interrupt Control Register INTCONTROLTable 11. EMAC Control Module Interrupt Control Register INTCONTROL FieldC0RXTHRESHEN-C2RXTHRESHEN CnRXTHRESHENCnRXTHRESHEN EMAC Control Module RegistersPage Page CnMISCEN CnMISCENField ValueC0RXTHRESHSTAT-C2RXTHRESHSTAT CnRXTHRESHSTATCnRXTHRESHSTAT EMAC Control Module RegistersPage Page CnMISCSTAT CnMISCSTATField ValueCnRXIMAX CnRXIMAXEMAC Control Module Registers FieldCnTXIMAX CnTXIMAXField Value4 MDIO Registers 4.1 MDIO Revision ID Register REVIDTable 22. Management Data Input/Output MDIO Registers Figure 25. MDIO Revision ID Register REVID4.2 MDIO Control Register CONTROL Figure 26. MDIO Control Register CONTROLTable 24. MDIO Control Register CONTROL Field Descriptions MDIO Registers4.3 PHY Acknowledge Status Register ALIVE 4.4 PHY Link Status Register LINKFigure 27. PHY Acknowledge Status Register ALIVE Table 25. PHY Acknowledge Status Register ALIVE Field Descriptions4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED Field Descriptions4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW Field DescriptionsField Descriptions Field Descriptions USERINTMASKCLEAR 4.10 MDIO User Command Complete Interrupt Mask Clear RegisterField Descriptions 4.11 MDIO User Access Register 0 USERACCESS0 Figure 35. MDIO User Access Register 0 USERACCESS0Table 33. MDIO User Access Register 0 USERACCESS0 Field Descriptions MDIO Registers4.12 MDIO User PHY Select Register 0 USERPHYSEL0 Figure 36. MDIO User PHY Select Register 0 USERPHYSEL0MDIO Registers Field4.13 MDIO User Access Register 1 USERACCESS1 Figure 37. MDIO User Access Register 1 USERACCESS1Table 35. MDIO User Access Register 1 USERACCESS1 Field Descriptions MDIO Registers4.14 MDIO User PHY Select Register 1 USERPHYSEL1 Figure 38. MDIO User PHY Select Register 1 USERPHYSEL1MDIO Registers FieldTable 37. Ethernet Media Access Controller EMAC Registers 5 EMAC Module RegistersEMAC Module Registers AcronymTable 37. Ethernet Media Access Controller EMAC Registers continued OffsetAcronym Register DescriptionTable 37. Ethernet Media Access Controller EMAC Registers continued OffsetAcronym Register Description5.1 Transmit Revision ID Register TXREVID 5.2 Transmit Control Register TXCONTROLFigure 39. Transmit Revision ID Register TXREVID Table 38. Transmit Revision ID Register TXREVID Field Descriptions5.3 Transmit Teardown Register TXTEARDOWN Figure 41. Transmit Teardown Register TXTEARDOWNTable 40. Transmit Teardown Register TXTEARDOWN Field Descriptions EMAC Module Registers5.4 Receive Revision ID Register RXREVID 5.5 Receive Control Register RXCONTROLFigure 42. Receive Revision ID Register RXREVID Table 41. Receive Revision ID Register RXREVID Field Descriptions5.6 Receive Teardown Register RXTEARDOWN Figure 44. Receive Teardown Register RXTEARDOWNTable 43. Receive Teardown Register RXTEARDOWN Field Descriptions EMAC Module Registers5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAW Figure 45. Transmit Interrupt Status Unmasked Register TXINTSTATRAWEMAC Module Registers Field5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKED Figure 46. Transmit Interrupt Status Masked Register TXINTSTATMASKEDEMAC Module Registers Field5.9 Transmit Interrupt Mask Set Register TXINTMASKSET Figure 47. Transmit Interrupt Mask Set Register TXINTMASKSETEMAC Module Registers Field5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR Figure 48. Transmit Interrupt Mask Clear Register TXINTMASKCLEAREMAC Module Registers Field5.11 MAC Input Vector Register MACINVECTOR Figure 49. MAC Input Vector Register MACINVECTORTable 48. MAC Input Vector Register MACINVECTOR Field Descriptions EMAC Module Registers5.12 MAC End Of Interrupt Vector Register MACEOIVECTOR Figure 50. MAC End Of Interrupt Vector Register MACEOIVECTOREMAC Module Registers Field5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAW Figure 51. Receive Interrupt Status Unmasked Register RXINTSTATRAWEMAC Module Registers Field5.14 Receive Interrupt Status Masked Register RXINTSTATMASKED Figure 52. Receive Interrupt Status Masked Register RXINTSTATMASKEDEMAC Module Registers Field5.15 Receive Interrupt Mask Set Register RXINTMASKSET Figure 53. Receive Interrupt Mask Set Register RXINTMASKSETEMAC Module Registers Field5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR Figure 54. Receive Interrupt Mask Clear Register RXINTMASKCLEAREMAC Module Registers Field5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW 5.18 MAC Interrupt Status Masked Register MACINTSTATMASKEDFigure 55. MAC Interrupt Status Unmasked Register MACINTSTATRAW Figure 56. MAC Interrupt Status Masked Register MACINTSTATMASKED5.19 MAC Interrupt Mask Set Register MACINTMASKSET 5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEARFigure 57. MAC Interrupt Mask Set Register MACINTMASKSET Figure 58. MAC Interrupt Mask Clear Register MACINTMASKCLEARRXMBPENABLE 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable RegisterField Descriptions Field Descriptions continued FieldValue DescriptionField Descriptions continued FieldValue Description5.22 Receive Unicast Enable Set Register RXUNICASTSET Figure 60. Receive Unicast Enable Set Register RXUNICASTSETEMAC Module Registers Field5.23 Receive Unicast Clear Register RXUNICASTCLEAR Figure 61. Receive Unicast Clear Register RXUNICASTCLEAREMAC Module Registers Field5.24 Receive Maximum Length Register RXMAXLEN 5.25 Receive Buffer Offset Register RXBUFFEROFFSETFigure 62. Receive Maximum Length Register RXMAXLEN Table 61. Receive Maximum Length Register RXMAXLEN Field Descriptions5.27 Receive Channel Flow Control Threshold Registers RX0FLOWTHRESH-RX7FLOWTHRESHField Descriptions Field DescriptionsFigure 66. Receive Channel n Free Buffer Count Register RXnFREEBUFFER EMAC Module RegistersField Description5.29 MAC Control Register MACCONTROL Figure 67. MAC Control Register MACCONTROLTable 66. MAC Control Register MACCONTROL Field Descriptions EMAC Module RegistersField ValueDescription Submit Documentation Feedback5.30 MAC Status Register MACSTATUS Figure 68. MAC Status Register MACSTATUSTable 67. MAC Status Register MACSTATUS Field Descriptions EMAC Module RegistersTable 67. MAC Status Register MACSTATUS Field Descriptions continued FieldValue Description5.31 Emulation Control Register EMCONTROL 5.32 FIFO Control Register FIFOCONTROLFigure 69. Emulation Control Register EMCONTROL Table 68. Emulation Control Register EMCONTROL Field Descriptions5.33 MAC Configuration Register MACCONFIG 5.34 Soft Reset Register SOFTRESETFigure 71. MAC Configuration Register MACCONFIG Table 70. MAC Configuration Register MACCONFIG Field Descriptions5.35 MAC Source Address Low Bytes Register MACSRCADDRLO 5.36 MAC Source Address High Bytes Register MACSRCADDRHIFigure 73. MAC Source Address Low Bytes Register MACSRCADDRLO Figure 74. MAC Source Address High Bytes Register MACSRCADDRHI5.37 MAC Hash Address Register 1 MACHASH1 5.38 MAC Hash Address Register 2 MACHASH2Figure 75. MAC Hash Address Register 1 MACHASH1 Table 74. MAC Hash Address Register 1 MACHASH1 Field Descriptions5.39 Back Off Test Register BOFFTEST 5.40 Transmit Pacing Algorithm Test Register TPACETESTFigure 77. Back Off Random Number Generator Test Register BOFFTEST Table 76. Back Off Test Register BOFFTEST Field Descriptions5.41 Receive Pause Timer Register RXPAUSE 5.42 Transmit Pause Timer Register TXPAUSEFigure 79. Receive Pause Timer Register RXPAUSE Table 78. Receive Pause Timer Register RXPAUSE Field Descriptions5.43 MAC Address Low Bytes Register MACADDRLO Figure 81. MAC Address Low Bytes Register MACADDRLOTable 80. MAC Address Low Bytes Register MACADDRLO Field Descriptions EMAC Module Registers5.44 MAC Address High Bytes Register MACADDRHI 5.45 MAC Index Register MACINDEXFigure 82. MAC Address High Bytes Register MACADDRHI Figure 83. MAC Index Register MACINDEX5.46 Transmit Channel DMA Head Descriptor Pointer Registers TX0HDP-TX7HDP 5.48 Transmit Channel Completion Pointer Registers TX0CP-TX7CP 5.49 Receive Channel Completion Pointer Registers RX0CP-RX7CPFigure 86. Transmit Channel n Completion Pointer Register TXnCP Figure 87. Receive Channel n Completion Pointer Register RXnCP5.50 Network Statistics Registers Figure 88. Statistics Register5.50.1 Good Receive Frames Register RXGOODFRAMES 5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS 5.50.5 Receive CRC Errors Register RXCRCERRORS5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.7 Receive Oversized Frames Register RXOVERSIZED 5.50.8 Receive Jabber Frames Register RXJABBER5.50.9 Receive Undersized Frames Register RXUNDERSIZED 5.50.10 Receive Frame Fragments Register RXFRAGMENTS5.50.13 Receive Octet Frames Register RXOCTETS 5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES 5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES 5.50.18 Deferred Transmit Frames Register TXDEFERRED5.50.24 Transmit Underrun Error Register TXUNDERRUN 5.50.20 Transmit Single Collision Frames Register TXSINGLECOLL5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL 5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL5.50.26 Transmit Octet Frames Register TXOCTETS 5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64 5.50.33 Network Octet Frames Register NETOCTETS 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS Appendix A Glossary Table 87. Physical Layer Definitions Appendix B Revision History Table 88. Document Revision HistoryReference Additions/Modifications/Deletions Submit Documentation FeedbackIMPORTANT NOTICE ProductsApplications TI E2E Community Home Page