EMAC Module Registers | www.ti.com |
5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)
The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 53 and described in Table 52.
Figure 53. Receive Interrupt Mask Set Register (RXINTMASKSET)
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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RX7THRESHMASK | RX6THRESHMASK | RX5THRESHMASK | RX4THRESHMASK | RX3THRESHMASK | RX2THRESHMASK | RX1THRESHMASK | RX0THRESHMASK |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RX7MASK | RX6MASK | RX5MASK | RX4MASK | RX3MASK | RX2MASK | RX1MASK | RX0MASK |
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LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect);
Table 52. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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15 | RX7THRESHMASK | Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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14 | RX6THRESHMASK | Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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13 | RX5THRESHMASK | Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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12 | RX4THRESHMASK | Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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11 | RX3THRESHMASK | Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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10 | RX2THRESHMASK | Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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9 | RX1THRESHMASK | Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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8 | RX0THRESHMASK | Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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7 | RX7MASK | Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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6 | RX6MASK | Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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5 | RX5MASK | Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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4 | RX4MASK | Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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3 | RX3MASK | Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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2 | RX2MASK | Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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1 | RX1MASK | Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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0 | RX0MASK | Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect. | |
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98 | EMAC/MDIO Module | SPRUFL5B |
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