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Texas Instruments TMS320C674X Receive Interrupt Mask Set Register RXINTMASKSET, Field, Value

Models: TMS320C674X

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5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)

EMAC Module Registers

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5.15 Receive Interrupt Mask Set Register (RXINTMASKSET)

The receive interrupt mask set register (RXINTMASKSET) is shown in Figure 53 and described in Table 52.

Figure 53. Receive Interrupt Mask Set Register (RXINTMASKSET)

31							16
			Reserved

			R-0
15	14	13	12	11	10	9	8

RX7THRESHMASK	RX6THRESHMASK	RX5THRESHMASK	RX4THRESHMASK	RX3THRESHMASK	RX2THRESHMASK	RX1THRESHMASK	RX0THRESHMASK

R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0
7	6	5	4	3	2	1	0

RX7MASK	RX6MASK	RX5MASK	RX4MASK	RX3MASK	RX2MASK	RX1MASK	RX0MASK
R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0	R/W1S-0

LEGEND: R/W = Read/Write; R = Read only; W1S = Write 1 to set (writing a 0 has no effect); -n= value after reset

Table 52. Receive Interrupt Mask Set Register (RXINTMASKSET) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	Reserved

15	RX7THRESHMASK	0-1	Receive channel 7 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

14	RX6THRESHMASK	0-1	Receive channel 6 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

13	RX5THRESHMASK	0-1	Receive channel 5 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

12	RX4THRESHMASK	0-1	Receive channel 4 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

11	RX3THRESHMASK	0-1	Receive channel 3 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

10	RX2THRESHMASK	0-1	Receive channel 2 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

9	RX1THRESHMASK	0-1	Receive channel 1 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

8	RX0THRESHMASK	0-1	Receive channel 0 threshold mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

7	RX7MASK	0-1	Receive channel 7 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

6	RX6MASK	0-1	Receive channel 6 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

5	RX5MASK	0-1	Receive channel 5 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

4	RX4MASK	0-1	Receive channel 4 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

3	RX3MASK	0-1	Receive channel 3 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

2	RX2MASK	0-1	Receive channel 2 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

1	RX1MASK	0-1	Receive channel 1 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

0	RX0MASK	0-1	Receive channel 0 mask set bit. Write 1 to enable interrupt; a write of 0 has no effect.

98	EMAC/MDIO Module	SPRUFL5B –April 2011
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Texas Instruments TMS320C674X manual Receive Interrupt Mask Set Register RXINTMASKSET, EMAC Module Registers, Field, Value

Contents

Management Data Input/Output MDIO Module TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller EMACUsers Guide SPRUFL5B -April Submit Documentation FeedbackPreface C0TXIMAX-C2TXIMAX Emulation Control Register EMCONTROL List of Figures Transmit Interrupt Mask Set Register TXINTMASKSET List of Tables List of TablesTransmit Interrupt Mask Set Register TXINTMASKSET Field Descriptions About This Manual Read This FirstPreface Notational ConventionsRelated Documentation From Texas Instruments Read This First1.2 Features EMAC/MDIO ModuleUsers Guide 1 Introduction1.3 Functional Block Diagram Figure 1. EMAC and MDIO Block Diagram2 Architecture 2.3 Signal Descriptions1.4 Industry Standards Compliance Statement 2.1 Clock ControlSignal Figure 2. Ethernet Configuration-MII ConnectionsTable 1. EMAC and MDIO Signals for MII Interface TypeTable 2. EMAC and MDIO Signals for RMII Interface Table 1. EMAC and MDIO Signals for MII Interface continuedFigure 3. Ethernet Configuration-RMII Connections 2.3.2 Reduced Media Independent Interface RMII ConnectionsFigure 4. Ethernet Frame Format 2.4 Ethernet Protocol Overview2.4.1 Ethernet Frame Format Table 3. Ethernet Frame Description2.5.1 Packet Buffer Descriptors 2.4.2 Ethernet’s Multiple Access Protocol2.5 Programming Interface Figure 5. Basic Descriptor FormatWord Offset Table 4. Basic Descriptor DescriptionFigure 6. Typical Descriptor Linked List 2.5.2 Transmit and Receive Descriptor Queues 2.5.3 Transmit and Receive EMAC Interrupts 2.5.4 Transmit Buffer Descriptor FormatNext Descriptor Pointer Figure 7. Transmit Buffer Descriptor FormatExample 1. Transmit Buffer Descriptor in C Structure Format Buffer Pointer2.5.4.3 Buffer Offset 2.5.4.1 Next Descriptor Pointer2.5.4.2 Buffer Pointer 2.5.4.4 Buffer Length2.5.4.9 End of Queue EOQ Flag 2.5.4.7 End of Packet EOP Flag2.5.4.8 Ownership OWNER Flag 2.5.4.10 Teardown Complete TDOWNCMPLT Flag2.5.5.2 Buffer Pointer 2.5.5 Receive Buffer Descriptor Format2.5.5.1 Next Descriptor Pointer Figure 8. Receive Buffer Descriptor FormatExample 2. Receive Buffer Descriptor in C Structure Format 2.5.5.3 Buffer Offset2.5.5.6 Start of Packet SOP Flag 2.5.5.4 Buffer Length2.5.5.5 Packet Length 2.5.5.7 End of Packet EOP Flag2.5.5.20 CRC Error CRCERROR Flag 2.5.5.18 Code Error CODEERROR Flag2.5.5.19 Alignment Error ALIGNERROR Flag 2.5.5.11 Pass CRC PASSCRC Flag2.6.1 Internal Memory Figure 9. EMAC Control Module Block Diagram2.6 EMAC Control Module 2.6.2 Bus Arbiter2.7.1 MDIO Module Components 2.7 MDIO Module2.6.3 Interrupt Control 2.7.1.1 MDIO Clock Generator Figure 10. MDIO Module Block Diagram2.7.1.4 PHY Register User Access 2.7.1.2 Global PHY Detection and Link State Monitoring2.7.2 MDIO Module Operational Overview 2.7.2.3 Reading Data From a PHY Register 2.7.2.1 Initializing the MDIO Module2.7.2.2 Writing Data To a PHY Register #define PHYREGreadregadr, phyadr 2.7.2.4 Example of MDIO Register Access CodeExample 3. MDIO Register Access Macros #define PHYREGwriteregadr, phyadr, data2.8.1 EMAC Module Components Figure 11. EMAC Module Block Diagram2.8 EMAC Module 2.8.1.1 Receive DMA Engine2.8.1.5 Transmit FIFO 2.8.1.11 Clock and Reset Logic2.8.1.4 Transmit DMA Engine 2.8.1.6 MAC Transmitter2.9.1.1 Receive Control 2.9 MAC Interface2.9.1 Data Reception 2.9.1.2 Receive Inter-Frame Interval2.9.1.3.1 Collision-Based Receive Buffer Flow Control 2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control2.9.2.2 CRC Insertion 2.9.2 Data Transmission2.9.2.1 Transmit Control 2.9.2.3 Adaptive Performance Optimization APO2.9.2.6 Transmit Flow Control 2.9.2.7 Speed, Duplex, and Pause Frame Support2.10.2 Receive Channel Enabling 2.10.1 Receive DMA Host Configuration2.10 Packet Receive Operation 2.10.3 Receive Address Matching2.10.6 Receive Channel Teardown 2.10.4 Hardware Receive QOS Support2.10.5 Host Free Buffer Tracking 2.10.7 Receive Frame Classification 2.10.8 Promiscuous Receive ModeRXCEFEN Table 5. Receive Frame Treatment SummaryRXCAFEN RXCMFEN2.10.9 Receive Overrun Table 6. Middle of Frame Overrun Treatment2.11.2 Transmit Channel Teardown 2.11.1 Transmit DMA Host Configuration2.11 Packet Transmit Operation 2.12 Receive and Transmit Latency 2.13 Transfer Node Priority2.14.2 Hardware Reset Considerations 2.14 Reset Considerations2.14.1 Software Reset Considerations 2.15.2 EMAC Control Module Initialization 2.15 Initialization2.15.1 Enabling the EMAC/MDIO Peripheral 2.15.3 MDIO Module Initialization2.15.4 EMAC Module Initialization 2.16.1.1 Transmit Packet Completion Interrupts 2.16 Interrupt Support2.16.1 EMAC Module Interrupt Events and Requests 2.16.1.2 Receive Packet Completion Interrupts2.16.1.4 Host Error Interrupt 2.16.1.3 Statistics Interrupt2.16.2.1 Link Change Interrupt 2.16.1.5 Receive Threshold Interrupts2.16.2 MDIO Module Interrupt Events and Requests 2.16.4 Interrupt Multiplexing 2.16.2.2 User Access Completion Interrupt2.16.3 Proper Interrupt Processing Table 7. Emulation Control 2.17 Power Management2.18 Emulation Considerations EMAC Control Module Registers 3 EMAC Control Module RegistersTable 8. EMAC Control Module Registers AcronymFigure 12. EMAC Control Module Revision ID Register REVID 3.1 EMAC Control Module Revision ID Register REVIDTable 8. EMAC Control Module Registers continued OffsetTable 10. EMAC Control Module Software Reset Register SOFTRESET 3.2 EMAC Control Module Software Reset Register SOFTRESETFigure 13. EMAC Control Module Software Reset Register SOFTRESET EMAC Control Module RegistersTable 11. EMAC Control Module Interrupt Control Register INTCONTROL 3.3 EMAC Control Module Interrupt Control Register INTCONTROLFigure 14. EMAC Control Module Interrupt Control Register INTCONTROL FieldCnRXTHRESHEN C0RXTHRESHEN-C2RXTHRESHENCnRXTHRESHEN EMAC Control Module RegistersPage Page Field CnMISCENCnMISCEN ValueCnRXTHRESHSTAT C0RXTHRESHSTAT-C2RXTHRESHSTATCnRXTHRESHSTAT EMAC Control Module RegistersPage Page Field CnMISCSTATCnMISCSTAT ValueEMAC Control Module Registers CnRXIMAXCnRXIMAX FieldField CnTXIMAXCnTXIMAX ValueTable 22. Management Data Input/Output MDIO Registers 4 MDIO Registers4.1 MDIO Revision ID Register REVID Figure 25. MDIO Revision ID Register REVIDTable 24. MDIO Control Register CONTROL Field Descriptions 4.2 MDIO Control Register CONTROLFigure 26. MDIO Control Register CONTROL MDIO RegistersFigure 27. PHY Acknowledge Status Register ALIVE 4.3 PHY Acknowledge Status Register ALIVE4.4 PHY Link Status Register LINK Table 25. PHY Acknowledge Status Register ALIVE Field Descriptions4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW Field Descriptions4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED Field Descriptions4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW Field DescriptionsField Descriptions Field Descriptions Field Descriptions 4.10 MDIO User Command Complete Interrupt Mask Clear RegisterUSERINTMASKCLEAR Table 33. MDIO User Access Register 0 USERACCESS0 Field Descriptions 4.11 MDIO User Access Register 0 USERACCESS0Figure 35. MDIO User Access Register 0 USERACCESS0 MDIO RegistersMDIO Registers 4.12 MDIO User PHY Select Register 0 USERPHYSEL0Figure 36. MDIO User PHY Select Register 0 USERPHYSEL0 FieldTable 35. MDIO User Access Register 1 USERACCESS1 Field Descriptions 4.13 MDIO User Access Register 1 USERACCESS1Figure 37. MDIO User Access Register 1 USERACCESS1 MDIO RegistersMDIO Registers 4.14 MDIO User PHY Select Register 1 USERPHYSEL1Figure 38. MDIO User PHY Select Register 1 USERPHYSEL1 FieldEMAC Module Registers Table 37. Ethernet Media Access Controller EMAC Registers5 EMAC Module Registers AcronymAcronym Table 37. Ethernet Media Access Controller EMAC Registers continuedOffset Register DescriptionAcronym Table 37. Ethernet Media Access Controller EMAC Registers continuedOffset Register DescriptionFigure 39. Transmit Revision ID Register TXREVID 5.1 Transmit Revision ID Register TXREVID5.2 Transmit Control Register TXCONTROL Table 38. Transmit Revision ID Register TXREVID Field DescriptionsTable 40. Transmit Teardown Register TXTEARDOWN Field Descriptions 5.3 Transmit Teardown Register TXTEARDOWNFigure 41. Transmit Teardown Register TXTEARDOWN EMAC Module RegistersFigure 42. Receive Revision ID Register RXREVID 5.4 Receive Revision ID Register RXREVID5.5 Receive Control Register RXCONTROL Table 41. Receive Revision ID Register RXREVID Field DescriptionsTable 43. Receive Teardown Register RXTEARDOWN Field Descriptions 5.6 Receive Teardown Register RXTEARDOWNFigure 44. Receive Teardown Register RXTEARDOWN EMAC Module RegistersEMAC Module Registers 5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAWFigure 45. Transmit Interrupt Status Unmasked Register TXINTSTATRAW FieldEMAC Module Registers 5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKEDFigure 46. Transmit Interrupt Status Masked Register TXINTSTATMASKED FieldEMAC Module Registers 5.9 Transmit Interrupt Mask Set Register TXINTMASKSETFigure 47. Transmit Interrupt Mask Set Register TXINTMASKSET FieldEMAC Module Registers 5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEARFigure 48. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR FieldTable 48. MAC Input Vector Register MACINVECTOR Field Descriptions 5.11 MAC Input Vector Register MACINVECTORFigure 49. MAC Input Vector Register MACINVECTOR EMAC Module RegistersEMAC Module Registers 5.12 MAC End Of Interrupt Vector Register MACEOIVECTORFigure 50. MAC End Of Interrupt Vector Register MACEOIVECTOR FieldEMAC Module Registers 5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAWFigure 51. Receive Interrupt Status Unmasked Register RXINTSTATRAW FieldEMAC Module Registers 5.14 Receive Interrupt Status Masked Register RXINTSTATMASKEDFigure 52. Receive Interrupt Status Masked Register RXINTSTATMASKED FieldEMAC Module Registers 5.15 Receive Interrupt Mask Set Register RXINTMASKSETFigure 53. Receive Interrupt Mask Set Register RXINTMASKSET FieldEMAC Module Registers 5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEARFigure 54. Receive Interrupt Mask Clear Register RXINTMASKCLEAR FieldFigure 55. MAC Interrupt Status Unmasked Register MACINTSTATRAW 5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED Figure 56. MAC Interrupt Status Masked Register MACINTSTATMASKEDFigure 57. MAC Interrupt Mask Set Register MACINTMASKSET 5.19 MAC Interrupt Mask Set Register MACINTMASKSET5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR Figure 58. MAC Interrupt Mask Clear Register MACINTMASKCLEARField Descriptions 5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable RegisterRXMBPENABLE Value Field Descriptions continuedField DescriptionValue Field Descriptions continuedField DescriptionEMAC Module Registers 5.22 Receive Unicast Enable Set Register RXUNICASTSETFigure 60. Receive Unicast Enable Set Register RXUNICASTSET FieldEMAC Module Registers 5.23 Receive Unicast Clear Register RXUNICASTCLEARFigure 61. Receive Unicast Clear Register RXUNICASTCLEAR FieldFigure 62. Receive Maximum Length Register RXMAXLEN 5.24 Receive Maximum Length Register RXMAXLEN5.25 Receive Buffer Offset Register RXBUFFEROFFSET Table 61. Receive Maximum Length Register RXMAXLEN Field DescriptionsField Descriptions 5.27 Receive Channel Flow Control Threshold RegistersRX0FLOWTHRESH-RX7FLOWTHRESH Field DescriptionsField Figure 66. Receive Channel n Free Buffer Count Register RXnFREEBUFFEREMAC Module Registers DescriptionTable 66. MAC Control Register MACCONTROL Field Descriptions 5.29 MAC Control Register MACCONTROLFigure 67. MAC Control Register MACCONTROL EMAC Module RegistersDescription FieldValue Submit Documentation FeedbackTable 67. MAC Status Register MACSTATUS Field Descriptions 5.30 MAC Status Register MACSTATUSFigure 68. MAC Status Register MACSTATUS EMAC Module RegistersValue Table 67. MAC Status Register MACSTATUS Field Descriptions continuedField DescriptionFigure 69. Emulation Control Register EMCONTROL 5.31 Emulation Control Register EMCONTROL5.32 FIFO Control Register FIFOCONTROL Table 68. Emulation Control Register EMCONTROL Field DescriptionsFigure 71. MAC Configuration Register MACCONFIG 5.33 MAC Configuration Register MACCONFIG5.34 Soft Reset Register SOFTRESET Table 70. MAC Configuration Register MACCONFIG Field DescriptionsFigure 73. MAC Source Address Low Bytes Register MACSRCADDRLO 5.35 MAC Source Address Low Bytes Register MACSRCADDRLO5.36 MAC Source Address High Bytes Register MACSRCADDRHI Figure 74. MAC Source Address High Bytes Register MACSRCADDRHIFigure 75. MAC Hash Address Register 1 MACHASH1 5.37 MAC Hash Address Register 1 MACHASH15.38 MAC Hash Address Register 2 MACHASH2 Table 74. MAC Hash Address Register 1 MACHASH1 Field DescriptionsFigure 77. Back Off Random Number Generator Test Register BOFFTEST 5.39 Back Off Test Register BOFFTEST5.40 Transmit Pacing Algorithm Test Register TPACETEST Table 76. Back Off Test Register BOFFTEST Field DescriptionsFigure 79. Receive Pause Timer Register RXPAUSE 5.41 Receive Pause Timer Register RXPAUSE5.42 Transmit Pause Timer Register TXPAUSE Table 78. Receive Pause Timer Register RXPAUSE Field DescriptionsTable 80. MAC Address Low Bytes Register MACADDRLO Field Descriptions 5.43 MAC Address Low Bytes Register MACADDRLOFigure 81. MAC Address Low Bytes Register MACADDRLO EMAC Module RegistersFigure 82. MAC Address High Bytes Register MACADDRHI 5.44 MAC Address High Bytes Register MACADDRHI5.45 MAC Index Register MACINDEX Figure 83. MAC Index Register MACINDEX5.46 Transmit Channel DMA Head Descriptor Pointer Registers TX0HDP-TX7HDP Figure 86. Transmit Channel n Completion Pointer Register TXnCP 5.48 Transmit Channel Completion Pointer Registers TX0CP-TX7CP5.49 Receive Channel Completion Pointer Registers RX0CP-RX7CP Figure 87. Receive Channel n Completion Pointer Register RXnCP5.50.1 Good Receive Frames Register RXGOODFRAMES 5.50 Network Statistics RegistersFigure 88. Statistics Register 5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.5 Receive CRC Errors Register RXCRCERRORS5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS 5.50.9 Receive Undersized Frames Register RXUNDERSIZED 5.50.7 Receive Oversized Frames Register RXOVERSIZED5.50.8 Receive Jabber Frames Register RXJABBER 5.50.10 Receive Frame Fragments Register RXFRAGMENTS5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED5.50.13 Receive Octet Frames Register RXOCTETS 5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES 5.50.18 Deferred Transmit Frames Register TXDEFERRED5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL 5.50.24 Transmit Underrun Error Register TXUNDERRUN5.50.20 Transmit Single Collision Frames Register TXSINGLECOLL 5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64 5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE5.50.26 Transmit Octet Frames Register TXOCTETS 5.50.33 Network Octet Frames Register NETOCTETS 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS Appendix A Glossary Table 87. Physical Layer Definitions Reference Additions/Modifications/Deletions Appendix B Revision HistoryTable 88. Document Revision History Submit Documentation FeedbackApplications IMPORTANT NOTICEProducts TI E2E Community Home Page