Texas Instruments TMS320C674X manual Transmit and Receive Emac Interrupts

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2.5.3Transmit and Receive EMAC Interrupts

The EMAC processes descriptors in linked list chains as discussed in Section 2.5.1, using the linked list queue mechanism discussed in Section 2.5.2.

The EMAC synchronizes descriptor list processing through the use of interrupts to the software application. The interrupts are controlled by the application using the interrupt masks, global interrupt enable, and the completion pointer register (CP). The CP is also called the interrupt acknowledge register.

The EMAC supports eight channels for transmit and eight channels for receive. The corresponding completion pointer registers are:

•TXnCP - Transmit Channel n Completion Pointer (Interrupt Acknowledge) Register

•RXnCP - Receive Channel n Completion Pointer (Interrupt Acknowledge) Register

These registers serve two purposes. When read, they return the pointer to the last descriptor that the EMAC has processed. When written by the software application, the value represents the last descriptor processed by the software application. When these two values do not match, the interrupt is active.

Interrupts in the EMAC control module are routed to three independent interrupt cores which are then mapped to CPU interrupt controllers. The system configuration determines whether or not an active interrupt actually interrupts the CPU. In general the following settings are required for basic EMAC transmit and receive interrupts:

1.EMAC transmit and receive interrupts are enabled by setting the mask registers RXINTMASKSET and

TXINTMASKSET

2.Global interrupts for the appropriate interrupt core registers are set in the EMAC control module: CnRXEN and CnTXEN on core n

3.The CPU interrupt controller is configured to accept Cn_RX_PULSE and Cn_TX_PULSE interrupts from the EMAC control module

Whether or not the interrupt is enabled, the current state of the receive or transmit channel interrupt can be examined directly by the software application reading the EMAC receive interrupt status (unmasked) register (RXINTSTATRAW) and transmit interrupt status (unmasked) register (TXINTSTATRAW).

After servicing transmit or receive interrupts, the application software must acknowledge both the EMAC and EMAC control module interrupts.

EMAC interrupts are acknowledged when the application software updates the value of TXnCP or RXnCP with a value that matches the internal value kept by the EMAC. This mechanism ensures that the application software never misses an EMAC interrupt because the interrupt acknowledgment is tied directly to the buffer descriptor processing.

EMAC control module interrupts are acknowledged when the application software writes the appropriate CnTX or CnRX key to the EMAC End-Of-Interrupt Vector register (MACEOIVECTOR). The MACEOIVECTOR behaves as an interrupt pulse interlock -- once the EMAC control module has issued an interrupt pulse to the CPU, it will not generate further pulses of the same type until the original pulse has been acknowledged.

2.5.4Transmit Buffer Descriptor Format

A transmit (TX) buffer descriptor (Figure 7) is a contiguous block of four 32-bit data words aligned on a 32-bit boundary that describes a packet or a packet fragment. Example 1 shows the transmit buffer descriptor described by a C structure.

SPRUFL5B –April 2011	EMAC/MDIO Module	21
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