Texas Instruments TMS320C674X guide

www.ti.com

EMAC Module Registers

5.28 Receive Channel Free Buffer Count Registers (RX0FREEBUFFER-RX7FREEBUFFER)

The receive channel 0-7 free buffer count register (RXnFREEBUFFER) is shown in Figure 66 and described in Table 65.

	Figure 66. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER)
31			16

			Reserved

			R-0
15			0

			RXnFREEBUF

			WI-0
LEGEND: R = Read only; WI = Write to increment; -n= value after reset
	Table 65. Receive Channel n Free Buffer Count Register (RXnFREEBUFFER) Field Descriptions

Bit	Field	Value	Description

31-16	Reserved	0	Reserved

15-0	RXnFREEBUF	0-FFh	Receive free buffer count. These bits contain the count of free buffers available. The
			RXFILTERTHRESH value is compared with this field to determine if low priority frames should be
			filtered. The RXnFLOWTHRESH value is compared with this field to determine if receive flow
			control should be issued against incoming packets (if enabled). This is a write-to-increment field.
			This field rolls over to 0 on overflow.
			If hardware flow control or QOS is used, the host must initialize this field to the number of available
			buffers (one register per channel). The EMAC decrements the associated channel register for each
			received frame by the number of buffers in the received frame. The host must write this field with
			the number of buffers that have been freed due to host processing.

SPRUFL5B –April 2011	EMAC/MDIO Module	109
Submit Documentation Feedback

© 2011, Texas Instruments Incorporated

Image 109

Texas Instruments TMS320C674X manual Receive Channel n Free Buffer Count Register RXnFREEBUFFER

Contents

Users Guide Submit Documentation Feedback C0MISCEN-C2MISCEN C0TXIMAX-C2TXIMAX Appendix B Appendix a List of Figures MAC Interrupt Mask Clear Register Macintmaskclear List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Industry Standards Compliance Statement Signal DescriptionsClock Control Memory Map Signal Type Description Emac and Mdio Signals for MII Interface Reduced Media Independent Interface Rmii Connections Emac and Mdio Signals for Rmii Interface Ethernet Frame Format Ethernet Protocol OverviewEthernet Frame Description Field Bytes Description Programming Interface Ethernet’s Multiple Access ProtocolPacket Buffer Descriptors Word Field Field Description Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit Buffer Descriptor Format Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Pointer Next Descriptor PointerBuffer Offset Buffer Length Ownership Owner Flag End of Packet EOP FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Alignment Error Alignerror Flag Code Error Codeerror FlagCRC Error Crcerror Flag Jabber Flag Internal Memory Emac Control ModuleBus Arbiter CPU Interrupt Control Mdio ModuleMdio Module Components Mdio Clock Generator PHY Register User AccessGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Mdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Emac Module Components Emac ModuleReceive DMA Engine Receive Fifo Transmit DMA Engine Clock and Reset LogicTransmit Fifo MAC Transmitter Data Reception MAC InterfaceReceive Control Receive Inter-Frame Interval Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control CRC Insertion Transmit ControlAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Speed, Duplex, and Pause Frame Support Transmit Flow Control Packet Receive Operation Receive DMA Host ConfigurationReceive Channel Enabling Receive Address Matching Host Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Receive Frame Classification Promiscuous Receive Mode Receive Frame Treatment Receive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationTransmit Channel Teardown Transfer Node Priority Receive and Transmit Latency Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Enabling the EMAC/MDIO Peripheral InitializationEmac Control Module Initialization Mdio Module Initialization Macintmaskset Emac Module Initialization Emac Module Interrupt Events and Requests Interrupt SupportTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Mdio Module Interrupt Events and Requests Receive Threshold InterruptsLink Change Interrupt Proper Interrupt Processing User Access Completion InterruptInterrupt Multiplexing Emulation Considerations Power ManagementEmulation Control Acronym Register Description Emac Control Module Registers Offset Acronym Register Description Emac Control Module Revision ID Register RevidBit Field Value Description Reset Emac Control Module Software Reset Register Softreset Intprescale Emac Control Module Interrupt Control Register IntcontrolC2TXPACEEN Bit Field RXCH7EN TXCH7EN Statpenden Statpenden Hostpenden LINKINT0EN USERINT0EN RXCH6THRESHSTAT RXCH7THRESHSTATRXCH5THRESHSTAT RXCH4THRESHSTAT RXCH7STAT TXCH7STAT Hostpendstat StatpendstatLINKINT0STAT USERINT0STAT Allowemacinterrupts Rximax Tximax Management Data Input/Output Mdio Registers Mdio Revision ID Register RevidMdio Revision ID Register Revid Field Descriptions Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link PHY Acknowledge Status Register AlivePHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions USERPHY1 USERPHY1 USERPHY0 Writing a 0 has no effect USERACCESS1 USERACCESS0 Effect W1S-0 Userintmaskclear Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Linkintenb Mdio User PHY Select Register 0 USERPHYSEL0Phyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Macstatus MacconfigEmcontrol Fifocontrol Network Statistics Registers Transmit Control Register Txcontrol Transmit Revision ID Register TxrevidTransmit Revision ID Register Txrevid Field Descriptions Transmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Control Register Rxcontrol Receive Revision ID Register RxrevidReceive Revision ID Register Rxrevid Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector Field Descriptions MAC Input Vector Register MacinvectorStatpend RX0THRESHPEND Intvect MAC End Of Interrupt Vector Register Maceoivector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Clear Register Macintmaskclear MAC Interrupt Mask Set Register MacintmasksetHostmask Statmask Hostmask Rxcmfen Rxpasscrc Rxqosen RxnochainRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Rxfilterthresh Receive Channel Flow Control Threshold Registers Receive Channel n Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Rxbufferflowen TxflowenLoopback Fullduplex MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Rxqosact Fifo Control Register Fifocontrol Emulation Control Register EmcontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions Soft Reset Register Softreset MAC Configuration Register MacconfigMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Transmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Transmit Pause Timer Register Txpause Receive Pause Timer Register RxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo Field Descriptions MAC Address Low Bytes Register MacaddrloValid Matchfilt Channel MACADDR0 MACADDR1 Valid MAC Index Register Macindex MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Receive Channel Completion Pointer Registers RX0CP-RX7CP Transmit Channel Completion Pointer Registers TX0CP-TX7CP Good Receive Frames Register Rxgoodframes Network Statistics RegistersBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Jabber Frames Register Rxjabber Receive Oversized Frames Register RxoversizedReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Multicast Transmit Frames Register Txmcastframes Broadcast Transmit Frames Register TxbcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Single Collision Frames Register Txsinglecoll Transmit Underrun Error Register TxunderrunTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Physical Layer Definitions Reference Additions/Modifications/Deletions Document Revision History DSP Products ApplicationsRfid TI E2E Community Home