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EMAC Module Registers

5.12 MAC End Of Interrupt Vector Register (MACEOIVECTOR)

The MAC end of interrupt vector register (MACEOIVECTOR) is shown in Figure 50 and described in Table 49.

Figure 50. MAC End Of Interrupt Vector Register (MACEOIVECTOR)

31			16
	Reserved

	R-0
15	5	4	0

Reserved			INTVECT

R-0			R/W-0

LEGEND: R/W = Read/Write; R = Read only; -n= value after reset

Table 49. MAC End Of Interrupt Vector Register (MACEOIVECTOR) Field Descriptions

Bit	Field	Value	Description

31-5	Reserved	0	Reserved

4-0	INTVECT	0-1Fh	Acknowledge EMAC Control Module Interrupts
		0h	Acknowledge C0RXTHRESH Interrupt
		1h	Acknowledge C0RX Interrupt
		2h	Acknowledge C0TX Interrupt
		3h	Acknowledge C0MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0)
		4h	Acknowledge C1RXTHRESH Interrupt
		5h	Acknowledge C1RX Interrupt
		6h	Acknowledge C1TX Interrupt
		7h	Acknowledge C1MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0)
		8h	Acknowledge C2RXTHRESH Interrupt
		9h	Acknowledge C2RX Interrupt
		Ah	Acknowledge C2TX Interrupt
		Bh	Acknowledge C2MISC Interrupt (STATPEND, HOSTPEND, MDIO LINKINT0, MDIO USERINT0)
		Ch-1Fh	Reserved

SPRUFL5B –April 2011	EMAC/MDIO Module	95
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Texas Instruments TMS320C674X manual MAC End Of Interrupt Vector Register Maceoivector, Intvect

Contents

Users Guide Submit Documentation Feedback C0MISCEN-C2MISCEN C0TXIMAX-C2TXIMAX Appendix B Appendix a List of Figures MAC Interrupt Mask Clear Register Macintmaskclear List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Purpose of the Peripheral Features Emac and Mdio Block Diagram Functional Block Diagram Memory Map Signal DescriptionsIndustry Standards Compliance Statement Clock Control Signal Type Description Emac and Mdio Signals for MII Interface Reduced Media Independent Interface Rmii Connections Emac and Mdio Signals for Rmii Interface Field Bytes Description Ethernet Protocol OverviewEthernet Frame Format Ethernet Frame Description Word Ethernet’s Multiple Access ProtocolProgramming Interface Packet Buffer Descriptors Field Field Description Basic Descriptor Description Transmit and Receive Descriptor Queues Transmit Buffer Descriptor Format Transmit and Receive Emac Interrupts Example 1. Transmit Buffer Descriptor in C Structure Format Transmit Buffer Descriptor Format Buffer Length Next Descriptor PointerBuffer Pointer Buffer Offset Teardown Complete Tdowncmplt Flag End of Packet EOP FlagOwnership Owner Flag End of Queue EOQ Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Jabber Flag Code Error Codeerror FlagAlignment Error Alignerror Flag CRC Error Crcerror Flag CPU Emac Control ModuleInternal Memory Bus Arbiter Mdio Module Components Mdio ModuleInterrupt Control Active PHY Monitoring PHY Register User AccessMdio Clock Generator Global PHY Detection and Link State Monitoring Mdio Module Operational Overview Reading Data From a PHY Register Initializing the Mdio ModuleWriting Data To a PHY Register Example 3. Mdio Register Access Macros Example of Mdio Register Access Code Receive Fifo Emac ModuleEmac Module Components Receive DMA Engine MAC Transmitter Clock and Reset LogicTransmit DMA Engine Transmit Fifo Receive Inter-Frame Interval MAC InterfaceData Reception Receive Control Ieee 802.3x-Based Receive Buffer Flow Control Collision-Based Receive Buffer Flow Control Interpacket-Gap IPG Enforcement Transmit ControlCRC Insertion Adaptive Performance Optimization APO Speed, Duplex, and Pause Frame Support Transmit Flow Control Receive Address Matching Receive DMA Host ConfigurationPacket Receive Operation Receive Channel Enabling Receive Channel Teardown Hardware Receive QOS SupportHost Free Buffer Tracking Receive Frame Classification Promiscuous Receive Mode Receive Frame Treatment Receive Frame Treatment Summary Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Transmit Channel Teardown Transmit DMA Host ConfigurationPacket Transmit Operation Transfer Node Priority Receive and Transmit Latency Hardware Reset Considerations Reset ConsiderationsSoftware Reset Considerations Mdio Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Emac Control Module Initialization Macintmaskset Emac Module Initialization Receive Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Transmit Packet Completion Interrupts Statistics Interrupt Host Error Interrupt Link Change Interrupt Receive Threshold InterruptsMdio Module Interrupt Events and Requests Interrupt Multiplexing User Access Completion InterruptProper Interrupt Processing Emulation Control Power ManagementEmulation Considerations Acronym Register Description Emac Control Module Registers Bit Field Value Description Emac Control Module Revision ID Register RevidOffset Acronym Register Description Reset Emac Control Module Software Reset Register Softreset C2TXPACEEN Emac Control Module Interrupt Control Register IntcontrolIntprescale Bit Field RXCH7EN TXCH7EN Statpenden Statpenden Hostpenden LINKINT0EN USERINT0EN RXCH4THRESHSTAT RXCH7THRESHSTATRXCH6THRESHSTAT RXCH5THRESHSTAT RXCH7STAT TXCH7STAT USERINT0STAT StatpendstatHostpendstat LINKINT0STAT Allowemacinterrupts Rximax Tximax Mdio Revision ID Register Revid Field Descriptions Mdio Revision ID Register RevidManagement Data Input/Output Mdio Registers Mdio Control Register Control Field Descriptions Mdio Control Register Control PHY Link Status Register Link Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Acknowledge Status Register Alive Field Descriptions USERPHY1 USERPHY1 USERPHY0 Writing a 0 has no effect USERACCESS1 USERACCESS0 Effect W1S-0 Userintmaskclear Mdio User Command Complete Interrupt Mask Clear Register Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User Access Register 0 USERACCESS0 Linksel Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Phyadrmon Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User Access Register 1 USERACCESS1 Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Fifocontrol MacconfigMacstatus Emcontrol Network Statistics Registers Transmit Control Register Txcontrol Field Descriptions Transmit Revision ID Register TxrevidTransmit Control Register Txcontrol Transmit Revision ID Register Txrevid Field Descriptions Txtdnch Transmit Teardown Register TxteardownTransmit Teardown Register Txteardown Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Revision ID Register RxrevidReceive Control Register Rxcontrol Receive Revision ID Register Rxrevid Field Descriptions Rxtdnch Receive Teardown Register RxteardownReceive Teardown Register Rxteardown Field Descriptions TX7PEND Transmit Interrupt Status Unmasked Register Txintstatraw Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked TX7MASK Transmit Interrupt Mask Set Register Txintmaskset Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear RX0THRESHPEND MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions Statpend Intvect MAC End Of Interrupt Vector Register Maceoivector Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear Hostpend Statpend MAC Interrupt Status Unmasked Register MacintstatrawMAC Interrupt Status Masked Register Macintstatmasked Hostmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Statmask Rxpromch Rxpasscrc Rxqosen RxnochainRxcmfen Rxcsfen Rxcefen Rxcafen Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Maximum Length Register Rxmaxlen Field Descriptions Receive Maximum Length Register RxmaxlenReceive Buffer Offset Register Rxbufferoffset Rxfilterthresh Receive Channel Flow Control Threshold Registers Receive Channel n Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol Field Descriptions MAC Control Register Maccontrol Fullduplex TxflowenRxbufferflowen Loopback MAC Status Register Macstatus Field Descriptions MAC Status Register Macstatus Rxqosact Fifo Control Register Fifocontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Emulation Control Register Emcontrol Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset MAC Configuration Register Macconfig Field Descriptions MAC Source Address High Bytes Register Macsrcaddrhi MAC Source Address Low Bytes Register Macsrcaddrlo MAC Hash Address Register 2 MACHASH2 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 1 MACHASH1 Field Descriptions Back Off Test Register Bofftest Field Descriptions Back Off Test Register BofftestTransmit Pacing Algorithm Test Register Tpacetest Transmit Pause Timer Register Txpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Receive Pause Timer Register Rxpause Field Descriptions Valid MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid Matchfilt Channel MACADDR0 MACADDR1 MACADDR2 MACADDR3 MACADDR4 MACADDR5 MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MAC Index Register Macindex Field Descriptions TXnHDP Receive Channel Completion Pointer Registers RX0CP-RX7CP Transmit Channel Completion Pointer Registers TX0CP-TX7CP Multicast Receive Frames Register Rxmcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Broadcast Receive Frames Register Rxbcastframes Pause Receive Frames Register Rxpauseframes Receive CRC Errors Register RxcrcerrorsReceive Alignment/Code Errors Register Rxaligncodeerrors Receive Frame Fragments Register Rxfragments Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Undersized Frames Register Rxundersized Good Transmit Frames Register Txgoodframes Receive QOS Filtered Frames Register RxqosfilteredReceive Octet Frames Register Rxoctets Deferred Transmit Frames Register Txdeferred Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Pause Transmit Frames Register Txpauseframes Transmit Late Collision Frames Register Txlatecoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Multiple Collision Frames Register Txmulticoll Transmit and Receive 64 Octet Frames Register FRAME64 Transmit Carrier Sense Errors Register TxcarriersenseTransmit Octet Frames Register Txoctets Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Term Definition Physical Layer Definitions Reference Additions/Modifications/Deletions Document Revision History TI E2E Community Home Products ApplicationsDSP Rfid