Effect | Texas Instruments TMS320C674X instruction

MDIO Registers

www.ti.com

4.8MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

The MDIO user command complete interrupt (masked) register (USERINTMASKED) is shown in Figure 32 and described in Table 30.

Figure 32. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

31			16
	Reserved

	R-0
15	2	1	0

Reserved		USERACCESS1	USERACCESS0

R-0		R/W1C-0	R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n= value after reset

Table 30. MDIO User Command Complete Interrupt (Masked) Register (USERINTMASKED)

Field Descriptions

Bit	Field	Value	Description

31-2	Reserved	0	Reserved

1	USERACCESS1		Masked value of MDIO User command complete interrupt. When asserted, The bit indicates
			that the previously scheduled PHY read or write command using that particular
			USERACCESS1 register has completed. Writing a 1 will clear the interrupt, writing a 0 has no
			effect.
		0	No MDIO user command complete event.
		1	The previously scheduled PHY read or write command using MDIO user access register
			USERACCESS1 has completed and the corresponding bit in USERINTMASKSET is set to 1.

0	USERACCESS0		Masked value of MDIO User command complete interrupt. When asserted, The bit indicates
			that the previously scheduled PHY read or write command using that particular
			USERACCESS0 register has completed. Writing a 1 will clear the interrupt, writing a 0 has no
			effect.
		0	No MDIO user command complete event.
		1	The previously scheduled PHY read or write command using MDIO user access register
			USERACCESS0 has completed and the corresponding bit in USERINTMASKSET is set to 1.

76	EMAC/MDIO Module	SPRUFL5B –April 2011
		Submit Documentation Feedback

© 2011, Texas Instruments Incorporated

Image 76

Texas Instruments TMS320C674X manual Effect

Contents

Users Guide Submit Documentation Feedback C0MISCEN-C2MISCEN C0TXIMAX-C2TXIMAX Appendix a Appendix B List of Figures MAC Interrupt Mask Clear Register Macintmaskclear List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Signal Descriptions Industry Standards Compliance StatementClock Control Memory Map Emac and Mdio Signals for MII Interface Signal Type Description Emac and Mdio Signals for Rmii Interface Reduced Media Independent Interface Rmii Connections Ethernet Protocol Overview Ethernet Frame FormatEthernet Frame Description Field Bytes Description Ethernet’s Multiple Access Protocol Programming InterfacePacket Buffer Descriptors Word Basic Descriptor Description Field Field Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Next Descriptor Pointer Buffer PointerBuffer Offset Buffer Length End of Packet EOP Flag Ownership Owner FlagEnd of Queue EOQ Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length Code Error Codeerror Flag Alignment Error Alignerror FlagCRC Error Crcerror Flag Jabber Flag Emac Control Module Internal MemoryBus Arbiter CPU Interrupt Control Mdio ModuleMdio Module Components PHY Register User Access Mdio Clock GeneratorGlobal PHY Detection and Link State Monitoring Active PHY Monitoring Mdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Emac Module Emac Module ComponentsReceive DMA Engine Receive Fifo Clock and Reset Logic Transmit DMA EngineTransmit Fifo MAC Transmitter MAC Interface Data ReceptionReceive Control Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Transmit Control CRC InsertionAdaptive Performance Optimization APO Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive DMA Host Configuration Packet Receive OperationReceive Channel Enabling Receive Address Matching Host Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Promiscuous Receive Mode Receive Frame Classification Receive Frame Treatment Summary Receive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationTransmit Channel Teardown Receive and Transmit Latency Transfer Node Priority Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Initialization Enabling the EMAC/MDIO PeripheralEmac Control Module Initialization Mdio Module Initialization Emac Module Initialization Macintmaskset Interrupt Support Emac Module Interrupt Events and RequestsTransmit Packet Completion Interrupts Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt Mdio Module Interrupt Events and Requests Receive Threshold InterruptsLink Change Interrupt Proper Interrupt Processing User Access Completion InterruptInterrupt Multiplexing Emulation Considerations Power ManagementEmulation Control Emac Control Module Registers Acronym Register Description Offset Acronym Register Description Emac Control Module Revision ID Register RevidBit Field Value Description Emac Control Module Software Reset Register Softreset Reset Intprescale Emac Control Module Interrupt Control Register IntcontrolC2TXPACEEN Bit Field RXCH7EN TXCH7EN Statpenden Hostpenden LINKINT0EN USERINT0EN Statpenden RXCH7THRESHSTAT RXCH6THRESHSTATRXCH5THRESHSTAT RXCH4THRESHSTAT RXCH7STAT TXCH7STAT Statpendstat HostpendstatLINKINT0STAT USERINT0STAT Rximax Allowemacinterrupts Tximax Management Data Input/Output Mdio Registers Mdio Revision ID Register RevidMdio Revision ID Register Revid Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive PHY Link Status Register LinkPHY Acknowledge Status Register Alive Field Descriptions PHY Link Status Register Link Field Descriptions USERPHY1 USERPHY0 USERPHY1 Writing a 0 has no effect USERACCESS1 USERACCESS0 Effect W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Mdio User PHY Select Register 0 USERPHYSEL0 Linksel LinkintenbPhyadrmon Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Macconfig MacstatusEmcontrol Fifocontrol Network Statistics Registers Transmit Revision ID Register Txrevid Transmit Control Register TxcontrolTransmit Revision ID Register Txrevid Field Descriptions Transmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Revision ID Register Rxrevid Receive Control Register RxcontrolReceive Revision ID Register Rxrevid Field Descriptions Receive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear MAC Input Vector Register Macinvector MAC Input Vector Register Macinvector Field DescriptionsStatpend RX0THRESHPEND MAC End Of Interrupt Vector Register Maceoivector Intvect Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend MAC Interrupt Mask Set Register Macintmaskset MAC Interrupt Mask Clear Register MacintmaskclearHostmask Statmask Hostmask Rxpasscrc Rxqosen Rxnochain RxcmfenRxcsfen Rxcefen Rxcafen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Channel Flow Control Threshold Registers Rxfilterthresh Receive Channel n Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Txflowen RxbufferflowenLoopback Fullduplex MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions Rxqosact Emulation Control Register Emcontrol Fifo Control Register FifocontrolEmulation Control Register Emcontrol Field Descriptions Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Soft Reset Register SoftresetMAC Configuration Register Macconfig Field Descriptions Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 MAC Hash Address Register 2 MACHASH2MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 2 MACHASH2 Field Descriptions Transmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Transmit Pause Timer Register TxpauseReceive Pause Timer Register Rxpause Field Descriptions Transmit Pause Timer Register Txpause Field Descriptions MAC Address Low Bytes Register Macaddrlo MAC Address Low Bytes Register Macaddrlo Field DescriptionsValid Matchfilt Channel MACADDR0 MACADDR1 Valid MAC Address High Bytes Register Macaddrhi MAC Index Register MacindexMAC Index Register Macindex Field Descriptions MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Transmit Channel Completion Pointer Registers TX0CP-TX7CP Receive Channel Completion Pointer Registers RX0CP-RX7CP Network Statistics Registers Good Receive Frames Register RxgoodframesBroadcast Receive Frames Register Rxbcastframes Multicast Receive Frames Register Rxmcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Oversized Frames Register Rxoversized Receive Jabber Frames Register RxjabberReceive Undersized Frames Register Rxundersized Receive Frame Fragments Register Rxfragments Receive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Broadcast Transmit Frames Register Txbcastframes Multicast Transmit Frames Register TxmcastframesPause Transmit Frames Register Txpauseframes Deferred Transmit Frames Register Txdeferred Transmit Underrun Error Register Txunderrun Transmit Single Collision Frames Register TxsinglecollTransmit Multiple Collision Frames Register Txmulticoll Transmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Physical Layer Definitions Term Definition Document Revision History Reference Additions/Modifications/Deletions Products Applications DSPRfid TI E2E Community Home