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TMS320C674X manual SPRUFL5B -April, Submit Documentation Feedback
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TMS320C674X
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Error codes
Functional Block Diagram
Ethernet Configuration-MII Connections
Clock and Reset Logic
MDIO User Command Complete Interrupt Unmasked Register USERINTRAW
Host Error Interrupt
Receive Pause Timer Register RXPAUSE
Signal Descriptions
Power Management
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
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SPRUFL5B
–April
2011
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© 2011, Texas Instruments Incorporated
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Contents
Management Data Input/Output MDIO Module
TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller EMAC
Users Guide
SPRUFL5B -April
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Preface
C0TXIMAX-C2TXIMAX
Emulation Control Register EMCONTROL
List of Figures
Transmit Interrupt Mask Set Register TXINTMASKSET
List of Tables
List of Tables
Transmit Interrupt Mask Set Register TXINTMASKSET Field Descriptions
About This Manual
Read This First
Preface
Notational Conventions
Related Documentation From Texas Instruments
Read This First
1.2 Features
EMAC/MDIO Module
Users Guide
1 Introduction
1.3 Functional Block Diagram
Figure 1. EMAC and MDIO Block Diagram
2 Architecture
2.3 Signal Descriptions
1.4 Industry Standards Compliance Statement
2.1 Clock Control
Signal
Figure 2. Ethernet Configuration-MII Connections
Table 1. EMAC and MDIO Signals for MII Interface
Type
Table 2. EMAC and MDIO Signals for RMII Interface
Table 1. EMAC and MDIO Signals for MII Interface continued
Figure 3. Ethernet Configuration-RMII Connections
2.3.2 Reduced Media Independent Interface RMII Connections
Figure 4. Ethernet Frame Format
2.4 Ethernet Protocol Overview
2.4.1 Ethernet Frame Format
Table 3. Ethernet Frame Description
2.5.1 Packet Buffer Descriptors
2.4.2 Ethernet’s Multiple Access Protocol
2.5 Programming Interface
Figure 5. Basic Descriptor Format
Word Offset
Table 4. Basic Descriptor Description
Figure 6. Typical Descriptor Linked List
2.5.2 Transmit and Receive Descriptor Queues
2.5.3 Transmit and Receive EMAC Interrupts
2.5.4 Transmit Buffer Descriptor Format
Next Descriptor Pointer
Figure 7. Transmit Buffer Descriptor Format
Example 1. Transmit Buffer Descriptor in C Structure Format
Buffer Pointer
2.5.4.3 Buffer Offset
2.5.4.1 Next Descriptor Pointer
2.5.4.2 Buffer Pointer
2.5.4.4 Buffer Length
2.5.4.9 End of Queue EOQ Flag
2.5.4.7 End of Packet EOP Flag
2.5.4.8 Ownership OWNER Flag
2.5.4.10 Teardown Complete TDOWNCMPLT Flag
2.5.5.2 Buffer Pointer
2.5.5 Receive Buffer Descriptor Format
2.5.5.1 Next Descriptor Pointer
Figure 8. Receive Buffer Descriptor Format
Example 2. Receive Buffer Descriptor in C Structure Format
2.5.5.3 Buffer Offset
2.5.5.6 Start of Packet SOP Flag
2.5.5.4 Buffer Length
2.5.5.5 Packet Length
2.5.5.7 End of Packet EOP Flag
2.5.5.20 CRC Error CRCERROR Flag
2.5.5.18 Code Error CODEERROR Flag
2.5.5.19 Alignment Error ALIGNERROR Flag
2.5.5.11 Pass CRC PASSCRC Flag
2.6.1 Internal Memory
Figure 9. EMAC Control Module Block Diagram
2.6 EMAC Control Module
2.6.2 Bus Arbiter
2.7.1 MDIO Module Components
2.7 MDIO Module
2.6.3 Interrupt Control
2.7.1.1 MDIO Clock Generator
Figure 10. MDIO Module Block Diagram
2.7.1.4 PHY Register User Access
2.7.1.2 Global PHY Detection and Link State Monitoring
2.7.2 MDIO Module Operational Overview
2.7.2.3 Reading Data From a PHY Register
2.7.2.1 Initializing the MDIO Module
2.7.2.2 Writing Data To a PHY Register
#define PHYREGreadregadr, phyadr
2.7.2.4 Example of MDIO Register Access Code
Example 3. MDIO Register Access Macros
#define PHYREGwriteregadr, phyadr, data
2.8.1 EMAC Module Components
Figure 11. EMAC Module Block Diagram
2.8 EMAC Module
2.8.1.1 Receive DMA Engine
2.8.1.5 Transmit FIFO
2.8.1.11 Clock and Reset Logic
2.8.1.4 Transmit DMA Engine
2.8.1.6 MAC Transmitter
2.9.1.1 Receive Control
2.9 MAC Interface
2.9.1 Data Reception
2.9.1.2 Receive Inter-Frame Interval
2.9.1.3.1 Collision-Based Receive Buffer Flow Control
2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control
2.9.2.2 CRC Insertion
2.9.2 Data Transmission
2.9.2.1 Transmit Control
2.9.2.3 Adaptive Performance Optimization APO
2.9.2.6 Transmit Flow Control
2.9.2.7 Speed, Duplex, and Pause Frame Support
2.10.2 Receive Channel Enabling
2.10.1 Receive DMA Host Configuration
2.10 Packet Receive Operation
2.10.3 Receive Address Matching
2.10.6 Receive Channel Teardown
2.10.4 Hardware Receive QOS Support
2.10.5 Host Free Buffer Tracking
2.10.7 Receive Frame Classification
2.10.8 Promiscuous Receive Mode
RXCEFEN
Table 5. Receive Frame Treatment Summary
RXCAFEN
RXCMFEN
2.10.9 Receive Overrun
Table 6. Middle of Frame Overrun Treatment
2.11.2 Transmit Channel Teardown
2.11.1 Transmit DMA Host Configuration
2.11 Packet Transmit Operation
2.12 Receive and Transmit Latency
2.13 Transfer Node Priority
2.14.2 Hardware Reset Considerations
2.14 Reset Considerations
2.14.1 Software Reset Considerations
2.15.2 EMAC Control Module Initialization
2.15 Initialization
2.15.1 Enabling the EMAC/MDIO Peripheral
2.15.3 MDIO Module Initialization
2.15.4 EMAC Module Initialization
2.16.1.1 Transmit Packet Completion Interrupts
2.16 Interrupt Support
2.16.1 EMAC Module Interrupt Events and Requests
2.16.1.2 Receive Packet Completion Interrupts
2.16.1.4 Host Error Interrupt
2.16.1.3 Statistics Interrupt
2.16.2.1 Link Change Interrupt
2.16.1.5 Receive Threshold Interrupts
2.16.2 MDIO Module Interrupt Events and Requests
2.16.4 Interrupt Multiplexing
2.16.2.2 User Access Completion Interrupt
2.16.3 Proper Interrupt Processing
Table 7. Emulation Control
2.17 Power Management
2.18 Emulation Considerations
EMAC Control Module Registers
3 EMAC Control Module Registers
Table 8. EMAC Control Module Registers
Acronym
Figure 12. EMAC Control Module Revision ID Register REVID
3.1 EMAC Control Module Revision ID Register REVID
Table 8. EMAC Control Module Registers continued
Offset
Table 10. EMAC Control Module Software Reset Register SOFTRESET
3.2 EMAC Control Module Software Reset Register SOFTRESET
Figure 13. EMAC Control Module Software Reset Register SOFTRESET
EMAC Control Module Registers
Table 11. EMAC Control Module Interrupt Control Register INTCONTROL
3.3 EMAC Control Module Interrupt Control Register INTCONTROL
Figure 14. EMAC Control Module Interrupt Control Register INTCONTROL
Field
CnRXTHRESHEN
C0RXTHRESHEN-C2RXTHRESHEN
CnRXTHRESHEN
EMAC Control Module Registers
Page
Page
Field
CnMISCEN
CnMISCEN
Value
CnRXTHRESHSTAT
C0RXTHRESHSTAT-C2RXTHRESHSTAT
CnRXTHRESHSTAT
EMAC Control Module Registers
Page
Page
Field
CnMISCSTAT
CnMISCSTAT
Value
EMAC Control Module Registers
CnRXIMAX
CnRXIMAX
Field
Field
CnTXIMAX
CnTXIMAX
Value
Table 22. Management Data Input/Output MDIO Registers
4 MDIO Registers
4.1 MDIO Revision ID Register REVID
Figure 25. MDIO Revision ID Register REVID
Table 24. MDIO Control Register CONTROL Field Descriptions
4.2 MDIO Control Register CONTROL
Figure 26. MDIO Control Register CONTROL
MDIO Registers
Figure 27. PHY Acknowledge Status Register ALIVE
4.3 PHY Acknowledge Status Register ALIVE
4.4 PHY Link Status Register LINK
Table 25. PHY Acknowledge Status Register ALIVE Field Descriptions
4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAW
Field Descriptions
4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKED
Field Descriptions
4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAW
Field Descriptions
Field Descriptions
Field Descriptions
Field Descriptions
4.10 MDIO User Command Complete Interrupt Mask Clear Register
USERINTMASKCLEAR
Table 33. MDIO User Access Register 0 USERACCESS0 Field Descriptions
4.11 MDIO User Access Register 0 USERACCESS0
Figure 35. MDIO User Access Register 0 USERACCESS0
MDIO Registers
MDIO Registers
4.12 MDIO User PHY Select Register 0 USERPHYSEL0
Figure 36. MDIO User PHY Select Register 0 USERPHYSEL0
Field
Table 35. MDIO User Access Register 1 USERACCESS1 Field Descriptions
4.13 MDIO User Access Register 1 USERACCESS1
Figure 37. MDIO User Access Register 1 USERACCESS1
MDIO Registers
MDIO Registers
4.14 MDIO User PHY Select Register 1 USERPHYSEL1
Figure 38. MDIO User PHY Select Register 1 USERPHYSEL1
Field
EMAC Module Registers
Table 37. Ethernet Media Access Controller EMAC Registers
5 EMAC Module Registers
Acronym
Acronym
Table 37. Ethernet Media Access Controller EMAC Registers continued
Offset
Register Description
Acronym
Table 37. Ethernet Media Access Controller EMAC Registers continued
Offset
Register Description
Figure 39. Transmit Revision ID Register TXREVID
5.1 Transmit Revision ID Register TXREVID
5.2 Transmit Control Register TXCONTROL
Table 38. Transmit Revision ID Register TXREVID Field Descriptions
Table 40. Transmit Teardown Register TXTEARDOWN Field Descriptions
5.3 Transmit Teardown Register TXTEARDOWN
Figure 41. Transmit Teardown Register TXTEARDOWN
EMAC Module Registers
Figure 42. Receive Revision ID Register RXREVID
5.4 Receive Revision ID Register RXREVID
5.5 Receive Control Register RXCONTROL
Table 41. Receive Revision ID Register RXREVID Field Descriptions
Table 43. Receive Teardown Register RXTEARDOWN Field Descriptions
5.6 Receive Teardown Register RXTEARDOWN
Figure 44. Receive Teardown Register RXTEARDOWN
EMAC Module Registers
EMAC Module Registers
5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAW
Figure 45. Transmit Interrupt Status Unmasked Register TXINTSTATRAW
Field
EMAC Module Registers
5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKED
Figure 46. Transmit Interrupt Status Masked Register TXINTSTATMASKED
Field
EMAC Module Registers
5.9 Transmit Interrupt Mask Set Register TXINTMASKSET
Figure 47. Transmit Interrupt Mask Set Register TXINTMASKSET
Field
EMAC Module Registers
5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAR
Figure 48. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR
Field
Table 48. MAC Input Vector Register MACINVECTOR Field Descriptions
5.11 MAC Input Vector Register MACINVECTOR
Figure 49. MAC Input Vector Register MACINVECTOR
EMAC Module Registers
EMAC Module Registers
5.12 MAC End Of Interrupt Vector Register MACEOIVECTOR
Figure 50. MAC End Of Interrupt Vector Register MACEOIVECTOR
Field
EMAC Module Registers
5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAW
Figure 51. Receive Interrupt Status Unmasked Register RXINTSTATRAW
Field
EMAC Module Registers
5.14 Receive Interrupt Status Masked Register RXINTSTATMASKED
Figure 52. Receive Interrupt Status Masked Register RXINTSTATMASKED
Field
EMAC Module Registers
5.15 Receive Interrupt Mask Set Register RXINTMASKSET
Figure 53. Receive Interrupt Mask Set Register RXINTMASKSET
Field
EMAC Module Registers
5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAR
Figure 54. Receive Interrupt Mask Clear Register RXINTMASKCLEAR
Field
Figure 55. MAC Interrupt Status Unmasked Register MACINTSTATRAW
5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAW
5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED
Figure 56. MAC Interrupt Status Masked Register MACINTSTATMASKED
Figure 57. MAC Interrupt Mask Set Register MACINTMASKSET
5.19 MAC Interrupt Mask Set Register MACINTMASKSET
5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR
Figure 58. MAC Interrupt Mask Clear Register MACINTMASKCLEAR
Field Descriptions
5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register
RXMBPENABLE
Value
Field Descriptions continued
Field
Description
Value
Field Descriptions continued
Field
Description
EMAC Module Registers
5.22 Receive Unicast Enable Set Register RXUNICASTSET
Figure 60. Receive Unicast Enable Set Register RXUNICASTSET
Field
EMAC Module Registers
5.23 Receive Unicast Clear Register RXUNICASTCLEAR
Figure 61. Receive Unicast Clear Register RXUNICASTCLEAR
Field
Figure 62. Receive Maximum Length Register RXMAXLEN
5.24 Receive Maximum Length Register RXMAXLEN
5.25 Receive Buffer Offset Register RXBUFFEROFFSET
Table 61. Receive Maximum Length Register RXMAXLEN Field Descriptions
Field Descriptions
5.27 Receive Channel Flow Control Threshold Registers
RX0FLOWTHRESH-RX7FLOWTHRESH
Field Descriptions
Field
Figure 66. Receive Channel n Free Buffer Count Register RXnFREEBUFFER
EMAC Module Registers
Description
Table 66. MAC Control Register MACCONTROL Field Descriptions
5.29 MAC Control Register MACCONTROL
Figure 67. MAC Control Register MACCONTROL
EMAC Module Registers
Description
Field
Value
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Table 67. MAC Status Register MACSTATUS Field Descriptions
5.30 MAC Status Register MACSTATUS
Figure 68. MAC Status Register MACSTATUS
EMAC Module Registers
Value
Table 67. MAC Status Register MACSTATUS Field Descriptions continued
Field
Description
Figure 69. Emulation Control Register EMCONTROL
5.31 Emulation Control Register EMCONTROL
5.32 FIFO Control Register FIFOCONTROL
Table 68. Emulation Control Register EMCONTROL Field Descriptions
Figure 71. MAC Configuration Register MACCONFIG
5.33 MAC Configuration Register MACCONFIG
5.34 Soft Reset Register SOFTRESET
Table 70. MAC Configuration Register MACCONFIG Field Descriptions
Figure 73. MAC Source Address Low Bytes Register MACSRCADDRLO
5.35 MAC Source Address Low Bytes Register MACSRCADDRLO
5.36 MAC Source Address High Bytes Register MACSRCADDRHI
Figure 74. MAC Source Address High Bytes Register MACSRCADDRHI
Figure 75. MAC Hash Address Register 1 MACHASH1
5.37 MAC Hash Address Register 1 MACHASH1
5.38 MAC Hash Address Register 2 MACHASH2
Table 74. MAC Hash Address Register 1 MACHASH1 Field Descriptions
Figure 77. Back Off Random Number Generator Test Register BOFFTEST
5.39 Back Off Test Register BOFFTEST
5.40 Transmit Pacing Algorithm Test Register TPACETEST
Table 76. Back Off Test Register BOFFTEST Field Descriptions
Figure 79. Receive Pause Timer Register RXPAUSE
5.41 Receive Pause Timer Register RXPAUSE
5.42 Transmit Pause Timer Register TXPAUSE
Table 78. Receive Pause Timer Register RXPAUSE Field Descriptions
Table 80. MAC Address Low Bytes Register MACADDRLO Field Descriptions
5.43 MAC Address Low Bytes Register MACADDRLO
Figure 81. MAC Address Low Bytes Register MACADDRLO
EMAC Module Registers
Figure 82. MAC Address High Bytes Register MACADDRHI
5.44 MAC Address High Bytes Register MACADDRHI
5.45 MAC Index Register MACINDEX
Figure 83. MAC Index Register MACINDEX
5.46 Transmit Channel DMA Head Descriptor Pointer Registers TX0HDP-TX7HDP
Figure 86. Transmit Channel n Completion Pointer Register TXnCP
5.48 Transmit Channel Completion Pointer Registers TX0CP-TX7CP
5.49 Receive Channel Completion Pointer Registers RX0CP-RX7CP
Figure 87. Receive Channel n Completion Pointer Register RXnCP
5.50.1 Good Receive Frames Register RXGOODFRAMES
5.50 Network Statistics Registers
Figure 88. Statistics Register
5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES
5.50.4 Pause Receive Frames Register RXPAUSEFRAMES
5.50.5 Receive CRC Errors Register RXCRCERRORS
5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS
5.50.9 Receive Undersized Frames Register RXUNDERSIZED
5.50.7 Receive Oversized Frames Register RXOVERSIZED
5.50.8 Receive Jabber Frames Register RXJABBER
5.50.10 Receive Frame Fragments Register RXFRAGMENTS
5.50.14 Good Transmit Frames Register TXGOODFRAMES
5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED
5.50.13 Receive Octet Frames Register RXOCTETS
5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES
5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES
5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES
5.50.18 Deferred Transmit Frames Register TXDEFERRED
5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL
5.50.24 Transmit Underrun Error Register TXUNDERRUN
5.50.20 Transmit Single Collision Frames Register TXSINGLECOLL
5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL
5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64
5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE
5.50.26 Transmit Octet Frames Register TXOCTETS
5.50.33 Network Octet Frames Register NETOCTETS
5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS
Appendix A Glossary
Table 87. Physical Layer Definitions
Reference Additions/Modifications/Deletions
Appendix B Revision History
Table 88. Document Revision History
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