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Texas Instruments TMS320C674X manual Receive Overrun, Middle of Frame Overrun Treatment

Models: TMS320C674X

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2.10.9Receive Overrun

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Architecture

2.10.9Receive Overrun

The types of receive overrun are:

•FIFO start of frame overrun (FIFO_SOF)

•FIFO middle of frame overrun (FIFO_MOF)

•DMA start of frame overrun (DMA_SOF)

•DMA middle of frame overrun (DMA_MOF)

The statistics counters used to track these types of receive overrun are:

•Receive start of frame overruns register (RXSOFOVERRUNS)

•Receive middle of frame overruns register (RXMOFOVERRUNS)

•Receive DMA overruns register (RXDMAOVERRUNS)

Start of frame overruns happen when there are no resources available when frame reception begins. Start of frame overruns increment the appropriate overrun statistic(s) and the frame is filtered.

Middle of frame overruns happen when there are some resources to start the frame reception, but the resources run out during frame reception. In normal operation, a frame that overruns after starting the frame reception is filtered and the appropriate statistic(s) are incremented; however, the RXCEFEN bit in the receive multicast/broadcast/promiscuous channel enable register (RXMBPENABLE) affects overrun frame treatment. Table 6 shows how the overrun condition is handled for the middle of frame overrun.

Table 6. Middle of Frame Overrun Treatment

Address Match	RXCAFEN	RXCEFEN	Middle of Frame Overrun Treatment
0	0	X	Overrun frame filtered.

0	1	0	Overrun frame filtered.

0	1	1	As much frame data as possible is transferred to the promiscuous channel
			until overrun. The appropriate overrun statistic(s) is incremented and the
			OVERRUN and NOMATCH flags are set in the SOP buffer descriptor. Note
			that the RXMAXLEN number of bytes cannot be reached for an overrun to
			occur (it would be truncated and be a jabber or oversize).

1	X	0	Overrun frame filtered with the appropriate overrun statistic(s) incremented.

1	X	1	As much frame data as possible is transferred to the address match
			channel until overrun. The appropriate overrun statistic(s) is incremented
			and the OVERRUN flag is set in the SOP buffer descriptor. Note that the
			RXMAXLEN number of bytes cannot be reached for an overrun to occur (it
			would be truncated).

SPRUFL5B –April 2011	EMAC/MDIO Module	45
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Texas Instruments TMS320C674X manual Receive Overrun, Middle of Frame Overrun Treatment

Contents

TMS320C674x/OMAP-L1x Processor Ethernet Media Access Controller EMAC Users GuideManagement Data Input/Output MDIO Module Submit Documentation Feedback SPRUFL5B -AprilPreface C0TXIMAX-C2TXIMAX Emulation Control Register EMCONTROL List of Figures Transmit Interrupt Mask Set Register TXINTMASKSET List of Tables List of TablesTransmit Interrupt Mask Set Register TXINTMASKSET Field Descriptions Preface Read This FirstAbout This Manual Notational ConventionsRead This First Related Documentation From Texas InstrumentsUsers Guide EMAC/MDIO Module1.2 Features 1 IntroductionFigure 1. EMAC and MDIO Block Diagram 1.3 Functional Block Diagram1.4 Industry Standards Compliance Statement 2.3 Signal Descriptions2 Architecture 2.1 Clock ControlTable 1. EMAC and MDIO Signals for MII Interface Figure 2. Ethernet Configuration-MII ConnectionsSignal TypeFigure 3. Ethernet Configuration-RMII Connections Table 1. EMAC and MDIO Signals for MII Interface continuedTable 2. EMAC and MDIO Signals for RMII Interface 2.3.2 Reduced Media Independent Interface RMII Connections2.4.1 Ethernet Frame Format 2.4 Ethernet Protocol OverviewFigure 4. Ethernet Frame Format Table 3. Ethernet Frame Description2.5 Programming Interface 2.4.2 Ethernet’s Multiple Access Protocol2.5.1 Packet Buffer Descriptors Figure 5. Basic Descriptor FormatTable 4. Basic Descriptor Description Figure 6. Typical Descriptor Linked ListWord Offset 2.5.2 Transmit and Receive Descriptor Queues 2.5.4 Transmit Buffer Descriptor Format 2.5.3 Transmit and Receive EMAC InterruptsExample 1. Transmit Buffer Descriptor in C Structure Format Figure 7. Transmit Buffer Descriptor FormatNext Descriptor Pointer Buffer Pointer2.5.4.2 Buffer Pointer 2.5.4.1 Next Descriptor Pointer2.5.4.3 Buffer Offset 2.5.4.4 Buffer Length2.5.4.8 Ownership OWNER Flag 2.5.4.7 End of Packet EOP Flag2.5.4.9 End of Queue EOQ Flag 2.5.4.10 Teardown Complete TDOWNCMPLT Flag2.5.5.1 Next Descriptor Pointer 2.5.5 Receive Buffer Descriptor Format2.5.5.2 Buffer Pointer Figure 8. Receive Buffer Descriptor Format2.5.5.3 Buffer Offset Example 2. Receive Buffer Descriptor in C Structure Format2.5.5.5 Packet Length 2.5.5.4 Buffer Length2.5.5.6 Start of Packet SOP Flag 2.5.5.7 End of Packet EOP Flag2.5.5.19 Alignment Error ALIGNERROR Flag 2.5.5.18 Code Error CODEERROR Flag2.5.5.20 CRC Error CRCERROR Flag 2.5.5.11 Pass CRC PASSCRC Flag2.6 EMAC Control Module Figure 9. EMAC Control Module Block Diagram2.6.1 Internal Memory 2.6.2 Bus Arbiter2.7 MDIO Module 2.6.3 Interrupt Control2.7.1 MDIO Module Components 2.7.1.4 PHY Register User Access Figure 10. MDIO Module Block Diagram2.7.1.1 MDIO Clock Generator 2.7.1.2 Global PHY Detection and Link State Monitoring2.7.2 MDIO Module Operational Overview 2.7.2.1 Initializing the MDIO Module 2.7.2.2 Writing Data To a PHY Register2.7.2.3 Reading Data From a PHY Register Example 3. MDIO Register Access Macros 2.7.2.4 Example of MDIO Register Access Code#define PHYREGreadregadr, phyadr #define PHYREGwriteregadr, phyadr, data2.8 EMAC Module Figure 11. EMAC Module Block Diagram2.8.1 EMAC Module Components 2.8.1.1 Receive DMA Engine2.8.1.4 Transmit DMA Engine 2.8.1.11 Clock and Reset Logic2.8.1.5 Transmit FIFO 2.8.1.6 MAC Transmitter2.9.1 Data Reception 2.9 MAC Interface2.9.1.1 Receive Control 2.9.1.2 Receive Inter-Frame Interval2.9.1.3.2 IEEE 802.3x-Based Receive Buffer Flow Control 2.9.1.3.1 Collision-Based Receive Buffer Flow Control2.9.2.1 Transmit Control 2.9.2 Data Transmission2.9.2.2 CRC Insertion 2.9.2.3 Adaptive Performance Optimization APO2.9.2.7 Speed, Duplex, and Pause Frame Support 2.9.2.6 Transmit Flow Control2.10 Packet Receive Operation 2.10.1 Receive DMA Host Configuration2.10.2 Receive Channel Enabling 2.10.3 Receive Address Matching2.10.4 Hardware Receive QOS Support 2.10.5 Host Free Buffer Tracking2.10.6 Receive Channel Teardown 2.10.8 Promiscuous Receive Mode 2.10.7 Receive Frame ClassificationRXCAFEN Table 5. Receive Frame Treatment SummaryRXCEFEN RXCMFENTable 6. Middle of Frame Overrun Treatment 2.10.9 Receive Overrun2.11.1 Transmit DMA Host Configuration 2.11 Packet Transmit Operation2.11.2 Transmit Channel Teardown 2.13 Transfer Node Priority 2.12 Receive and Transmit Latency2.14 Reset Considerations 2.14.1 Software Reset Considerations2.14.2 Hardware Reset Considerations 2.15.1 Enabling the EMAC/MDIO Peripheral 2.15 Initialization2.15.2 EMAC Control Module Initialization 2.15.3 MDIO Module Initialization2.15.4 EMAC Module Initialization 2.16.1 EMAC Module Interrupt Events and Requests 2.16 Interrupt Support2.16.1.1 Transmit Packet Completion Interrupts 2.16.1.2 Receive Packet Completion Interrupts2.16.1.3 Statistics Interrupt 2.16.1.4 Host Error Interrupt2.16.1.5 Receive Threshold Interrupts 2.16.2 MDIO Module Interrupt Events and Requests2.16.2.1 Link Change Interrupt 2.16.2.2 User Access Completion Interrupt 2.16.3 Proper Interrupt Processing2.16.4 Interrupt Multiplexing 2.17 Power Management 2.18 Emulation ConsiderationsTable 7. Emulation Control Table 8. EMAC Control Module Registers 3 EMAC Control Module RegistersEMAC Control Module Registers AcronymTable 8. EMAC Control Module Registers continued 3.1 EMAC Control Module Revision ID Register REVIDFigure 12. EMAC Control Module Revision ID Register REVID OffsetFigure 13. EMAC Control Module Software Reset Register SOFTRESET 3.2 EMAC Control Module Software Reset Register SOFTRESETTable 10. EMAC Control Module Software Reset Register SOFTRESET EMAC Control Module RegistersFigure 14. EMAC Control Module Interrupt Control Register INTCONTROL 3.3 EMAC Control Module Interrupt Control Register INTCONTROLTable 11. EMAC Control Module Interrupt Control Register INTCONTROL FieldCnRXTHRESHEN C0RXTHRESHEN-C2RXTHRESHENCnRXTHRESHEN EMAC Control Module RegistersPage Page CnMISCEN CnMISCENField ValueCnRXTHRESHSTAT C0RXTHRESHSTAT-C2RXTHRESHSTATCnRXTHRESHSTAT EMAC Control Module RegistersPage Page CnMISCSTAT CnMISCSTATField ValueCnRXIMAX CnRXIMAXEMAC Control Module Registers FieldCnTXIMAX CnTXIMAXField Value4.1 MDIO Revision ID Register REVID 4 MDIO RegistersTable 22. Management Data Input/Output MDIO Registers Figure 25. MDIO Revision ID Register REVIDFigure 26. MDIO Control Register CONTROL 4.2 MDIO Control Register CONTROLTable 24. MDIO Control Register CONTROL Field Descriptions MDIO Registers4.4 PHY Link Status Register LINK 4.3 PHY Acknowledge Status Register ALIVEFigure 27. PHY Acknowledge Status Register ALIVE Table 25. PHY Acknowledge Status Register ALIVE Field DescriptionsField Descriptions 4.5 MDIO Link Status Change Interrupt Unmasked Register LINKINTRAWField Descriptions 4.6 MDIO Link Status Change Interrupt Masked Register LINKINTMASKEDField Descriptions 4.7 MDIO User Command Complete Interrupt Unmasked Register USERINTRAWField Descriptions Field Descriptions 4.10 MDIO User Command Complete Interrupt Mask Clear Register USERINTMASKCLEARField Descriptions Figure 35. MDIO User Access Register 0 USERACCESS0 4.11 MDIO User Access Register 0 USERACCESS0Table 33. MDIO User Access Register 0 USERACCESS0 Field Descriptions MDIO RegistersFigure 36. MDIO User PHY Select Register 0 USERPHYSEL0 4.12 MDIO User PHY Select Register 0 USERPHYSEL0MDIO Registers FieldFigure 37. MDIO User Access Register 1 USERACCESS1 4.13 MDIO User Access Register 1 USERACCESS1Table 35. MDIO User Access Register 1 USERACCESS1 Field Descriptions MDIO RegistersFigure 38. MDIO User PHY Select Register 1 USERPHYSEL1 4.14 MDIO User PHY Select Register 1 USERPHYSEL1MDIO Registers Field5 EMAC Module Registers Table 37. Ethernet Media Access Controller EMAC RegistersEMAC Module Registers AcronymOffset Table 37. Ethernet Media Access Controller EMAC Registers continuedAcronym Register DescriptionOffset Table 37. Ethernet Media Access Controller EMAC Registers continuedAcronym Register Description5.2 Transmit Control Register TXCONTROL 5.1 Transmit Revision ID Register TXREVIDFigure 39. Transmit Revision ID Register TXREVID Table 38. Transmit Revision ID Register TXREVID Field DescriptionsFigure 41. Transmit Teardown Register TXTEARDOWN 5.3 Transmit Teardown Register TXTEARDOWNTable 40. Transmit Teardown Register TXTEARDOWN Field Descriptions EMAC Module Registers5.5 Receive Control Register RXCONTROL 5.4 Receive Revision ID Register RXREVIDFigure 42. Receive Revision ID Register RXREVID Table 41. Receive Revision ID Register RXREVID Field DescriptionsFigure 44. Receive Teardown Register RXTEARDOWN 5.6 Receive Teardown Register RXTEARDOWNTable 43. Receive Teardown Register RXTEARDOWN Field Descriptions EMAC Module RegistersFigure 45. Transmit Interrupt Status Unmasked Register TXINTSTATRAW 5.7 Transmit Interrupt Status Unmasked Register TXINTSTATRAWEMAC Module Registers FieldFigure 46. Transmit Interrupt Status Masked Register TXINTSTATMASKED 5.8 Transmit Interrupt Status Masked Register TXINTSTATMASKEDEMAC Module Registers FieldFigure 47. Transmit Interrupt Mask Set Register TXINTMASKSET 5.9 Transmit Interrupt Mask Set Register TXINTMASKSETEMAC Module Registers FieldFigure 48. Transmit Interrupt Mask Clear Register TXINTMASKCLEAR 5.10 Transmit Interrupt Mask Clear Register TXINTMASKCLEAREMAC Module Registers FieldFigure 49. MAC Input Vector Register MACINVECTOR 5.11 MAC Input Vector Register MACINVECTORTable 48. MAC Input Vector Register MACINVECTOR Field Descriptions EMAC Module RegistersFigure 50. MAC End Of Interrupt Vector Register MACEOIVECTOR 5.12 MAC End Of Interrupt Vector Register MACEOIVECTOREMAC Module Registers FieldFigure 51. Receive Interrupt Status Unmasked Register RXINTSTATRAW 5.13 Receive Interrupt Status Unmasked Register RXINTSTATRAWEMAC Module Registers FieldFigure 52. Receive Interrupt Status Masked Register RXINTSTATMASKED 5.14 Receive Interrupt Status Masked Register RXINTSTATMASKEDEMAC Module Registers FieldFigure 53. Receive Interrupt Mask Set Register RXINTMASKSET 5.15 Receive Interrupt Mask Set Register RXINTMASKSETEMAC Module Registers FieldFigure 54. Receive Interrupt Mask Clear Register RXINTMASKCLEAR 5.16 Receive Interrupt Mask Clear Register RXINTMASKCLEAREMAC Module Registers Field5.18 MAC Interrupt Status Masked Register MACINTSTATMASKED 5.17 MAC Interrupt Status Unmasked Register MACINTSTATRAWFigure 55. MAC Interrupt Status Unmasked Register MACINTSTATRAW Figure 56. MAC Interrupt Status Masked Register MACINTSTATMASKED5.20 MAC Interrupt Mask Clear Register MACINTMASKCLEAR 5.19 MAC Interrupt Mask Set Register MACINTMASKSETFigure 57. MAC Interrupt Mask Set Register MACINTMASKSET Figure 58. MAC Interrupt Mask Clear Register MACINTMASKCLEAR5.21 Receive Multicast/Broadcast/Promiscuous Channel Enable Register RXMBPENABLEField Descriptions Field Field Descriptions continuedValue DescriptionField Field Descriptions continuedValue DescriptionFigure 60. Receive Unicast Enable Set Register RXUNICASTSET 5.22 Receive Unicast Enable Set Register RXUNICASTSETEMAC Module Registers FieldFigure 61. Receive Unicast Clear Register RXUNICASTCLEAR 5.23 Receive Unicast Clear Register RXUNICASTCLEAREMAC Module Registers Field5.25 Receive Buffer Offset Register RXBUFFEROFFSET 5.24 Receive Maximum Length Register RXMAXLENFigure 62. Receive Maximum Length Register RXMAXLEN Table 61. Receive Maximum Length Register RXMAXLEN Field DescriptionsRX0FLOWTHRESH-RX7FLOWTHRESH 5.27 Receive Channel Flow Control Threshold RegistersField Descriptions Field DescriptionsEMAC Module Registers Figure 66. Receive Channel n Free Buffer Count Register RXnFREEBUFFERField DescriptionFigure 67. MAC Control Register MACCONTROL 5.29 MAC Control Register MACCONTROLTable 66. MAC Control Register MACCONTROL Field Descriptions EMAC Module RegistersValue FieldDescription Submit Documentation FeedbackFigure 68. MAC Status Register MACSTATUS 5.30 MAC Status Register MACSTATUSTable 67. MAC Status Register MACSTATUS Field Descriptions EMAC Module RegistersField Table 67. MAC Status Register MACSTATUS Field Descriptions continuedValue Description5.32 FIFO Control Register FIFOCONTROL 5.31 Emulation Control Register EMCONTROLFigure 69. Emulation Control Register EMCONTROL Table 68. Emulation Control Register EMCONTROL Field Descriptions5.34 Soft Reset Register SOFTRESET 5.33 MAC Configuration Register MACCONFIGFigure 71. MAC Configuration Register MACCONFIG Table 70. MAC Configuration Register MACCONFIG Field Descriptions5.36 MAC Source Address High Bytes Register MACSRCADDRHI 5.35 MAC Source Address Low Bytes Register MACSRCADDRLOFigure 73. MAC Source Address Low Bytes Register MACSRCADDRLO Figure 74. MAC Source Address High Bytes Register MACSRCADDRHI5.38 MAC Hash Address Register 2 MACHASH2 5.37 MAC Hash Address Register 1 MACHASH1Figure 75. MAC Hash Address Register 1 MACHASH1 Table 74. MAC Hash Address Register 1 MACHASH1 Field Descriptions5.40 Transmit Pacing Algorithm Test Register TPACETEST 5.39 Back Off Test Register BOFFTESTFigure 77. Back Off Random Number Generator Test Register BOFFTEST Table 76. Back Off Test Register BOFFTEST Field Descriptions5.42 Transmit Pause Timer Register TXPAUSE 5.41 Receive Pause Timer Register RXPAUSEFigure 79. Receive Pause Timer Register RXPAUSE Table 78. Receive Pause Timer Register RXPAUSE Field DescriptionsFigure 81. MAC Address Low Bytes Register MACADDRLO 5.43 MAC Address Low Bytes Register MACADDRLOTable 80. MAC Address Low Bytes Register MACADDRLO Field Descriptions EMAC Module Registers5.45 MAC Index Register MACINDEX 5.44 MAC Address High Bytes Register MACADDRHIFigure 82. MAC Address High Bytes Register MACADDRHI Figure 83. MAC Index Register MACINDEX5.46 Transmit Channel DMA Head Descriptor Pointer Registers TX0HDP-TX7HDP 5.49 Receive Channel Completion Pointer Registers RX0CP-RX7CP 5.48 Transmit Channel Completion Pointer Registers TX0CP-TX7CPFigure 86. Transmit Channel n Completion Pointer Register TXnCP Figure 87. Receive Channel n Completion Pointer Register RXnCPFigure 88. Statistics Register 5.50 Network Statistics Registers5.50.1 Good Receive Frames Register RXGOODFRAMES 5.50.2 Broadcast Receive Frames Register RXBCASTFRAMES5.50.5 Receive CRC Errors Register RXCRCERRORS 5.50.6 Receive Alignment/Code Errors Register RXALIGNCODEERRORS5.50.4 Pause Receive Frames Register RXPAUSEFRAMES 5.50.8 Receive Jabber Frames Register RXJABBER 5.50.7 Receive Oversized Frames Register RXOVERSIZED5.50.9 Receive Undersized Frames Register RXUNDERSIZED 5.50.10 Receive Frame Fragments Register RXFRAGMENTS5.50.12 Receive QOS Filtered Frames Register RXQOSFILTERED 5.50.13 Receive Octet Frames Register RXOCTETS5.50.14 Good Transmit Frames Register TXGOODFRAMES 5.50.16 Multicast Transmit Frames Register TXMCASTFRAMES 5.50.15 Broadcast Transmit Frames Register TXBCASTFRAMES5.50.17 Pause Transmit Frames Register TXPAUSEFRAMES 5.50.18 Deferred Transmit Frames Register TXDEFERRED5.50.20 Transmit Single Collision Frames Register TXSINGLECOLL 5.50.24 Transmit Underrun Error Register TXUNDERRUN5.50.21 Transmit Multiple Collision Frames Register TXMULTICOLL 5.50.22 Transmit Excessive Collision Frames Register TXEXCESSIVECOLL5.50.25 Transmit Carrier Sense Errors Register TXCARRIERSENSE 5.50.26 Transmit Octet Frames Register TXOCTETS5.50.27 Transmit and Receive 64 Octet Frames Register FRAME64 5.50.33 Network Octet Frames Register NETOCTETS 5.50.36 Receive DMA Overruns Register RXDMAOVERRUNS Appendix A Glossary Table 87. Physical Layer Definitions Table 88. Document Revision History Appendix B Revision HistoryReference Additions/Modifications/Deletions Submit Documentation FeedbackProducts IMPORTANT NOTICEApplications TI E2E Community Home Page