Texas Instruments TMS320C674X instruction

EMAC Module Registers

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5.23 Receive Unicast Clear Register (RXUNICASTCLEAR)

The receive unicast clear register (RXUNICASTCLEAR) is shown in Figure 61 and described in Table 60.

		Figure 61. Receive Unicast Clear Register (RXUNICASTCLEAR)
31									16

				Reserved

					R-0
15									8

				Reserved

					R-0
7	6	5		4	3		2	1	0

RXCH7EN	RXCH6EN		RXCH5EN	RXCH4EN		RXCH3EN	RXCH2EN	RXCH1EN	RXCH0EN
R/W1C-0	R/W1C-0		R/W1C-0	R/W1C-0		R/W1C-0	R/W1C-0	R/W1C-0	R/W1C-0

LEGEND: R/W = Read/Write; R = Read only; W1C = Write 1 to clear (writing a 0 has no effect); -n= value after reset

Table 60. Receive Unicast Clear Register (RXUNICASTCLEAR) Field Descriptions

Bit	Field	Value	Description

31-8	Reserved	0	Reserved

7	RXCH7EN	0-1	Receive channel 7 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

6	RXCH6EN	0-1	Receive channel 6 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

5	RXCH5EN	0-1	Receive channel 5 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

4	RXCH4EN	0-1	Receive channel 4 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

3	RXCH3EN	0-1	Receive channel 3 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

2	RXCH2EN	0-1	Receive channel 2 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

1	RXCH1EN	0-1	Receive channel 1 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

0	RXCH0EN	0-1	Receive channel 0 unicast enable clear bit. Write 1 to clear the enable, a write of 0 has no effect.

106	EMAC/MDIO Module	SPRUFL5B –April 2011
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Texas Instruments TMS320C674X manual Receive Unicast Clear Register Rxunicastclear

Contents

Users Guide Submit Documentation Feedback C0MISCEN-C2MISCEN C0TXIMAX-C2TXIMAX Appendix a Appendix B List of Figures MAC Interrupt Mask Clear Register Macintmaskclear List of Tables MAC Control Register Maccontrol Field Descriptions Read This First Related Documentation From Texas Instruments Features Purpose of the Peripheral Functional Block Diagram Emac and Mdio Block Diagram Clock Control Signal DescriptionsIndustry Standards Compliance Statement Memory Map Emac and Mdio Signals for MII Interface Signal Type Description Emac and Mdio Signals for Rmii Interface Reduced Media Independent Interface Rmii Connections Ethernet Frame Description Ethernet Protocol OverviewEthernet Frame Format Field Bytes Description Packet Buffer Descriptors Ethernet’s Multiple Access ProtocolProgramming Interface Word Basic Descriptor Description Field Field Description Transmit and Receive Descriptor Queues Transmit and Receive Emac Interrupts Transmit Buffer Descriptor Format Transmit Buffer Descriptor Format Example 1. Transmit Buffer Descriptor in C Structure Format Buffer Offset Next Descriptor PointerBuffer Pointer Buffer Length End of Queue EOQ Flag End of Packet EOP FlagOwnership Owner Flag Teardown Complete Tdowncmplt Flag Receive Buffer Descriptor Format Receive Buffer Descriptor Format Example 2. Receive Buffer Descriptor in C Structure Format Buffer Length CRC Error Crcerror Flag Code Error Codeerror FlagAlignment Error Alignerror Flag Jabber Flag Bus Arbiter Emac Control ModuleInternal Memory CPU Interrupt Control Mdio ModuleMdio Module Components Global PHY Detection and Link State Monitoring PHY Register User AccessMdio Clock Generator Active PHY Monitoring Mdio Module Operational Overview Writing Data To a PHY Register Initializing the Mdio ModuleReading Data From a PHY Register Example of Mdio Register Access Code Example 3. Mdio Register Access Macros Receive DMA Engine Emac ModuleEmac Module Components Receive Fifo Transmit Fifo Clock and Reset LogicTransmit DMA Engine MAC Transmitter Receive Control MAC InterfaceData Reception Receive Inter-Frame Interval Collision-Based Receive Buffer Flow Control Ieee 802.3x-Based Receive Buffer Flow Control Adaptive Performance Optimization APO Transmit ControlCRC Insertion Interpacket-Gap IPG Enforcement Transmit Flow Control Speed, Duplex, and Pause Frame Support Receive Channel Enabling Receive DMA Host ConfigurationPacket Receive Operation Receive Address Matching Host Free Buffer Tracking Hardware Receive QOS SupportReceive Channel Teardown Promiscuous Receive Mode Receive Frame Classification Receive Frame Treatment Summary Receive Frame Treatment Middle of Frame Overrun Treatment Receive OverrunMiddle of Frame Overrun Treatment Packet Transmit Operation Transmit DMA Host ConfigurationTransmit Channel Teardown Receive and Transmit Latency Transfer Node Priority Software Reset Considerations Reset ConsiderationsHardware Reset Considerations Emac Control Module Initialization InitializationEnabling the EMAC/MDIO Peripheral Mdio Module Initialization Emac Module Initialization Macintmaskset Transmit Packet Completion Interrupts Interrupt SupportEmac Module Interrupt Events and Requests Receive Packet Completion Interrupts Host Error Interrupt Statistics Interrupt Mdio Module Interrupt Events and Requests Receive Threshold InterruptsLink Change Interrupt Proper Interrupt Processing User Access Completion InterruptInterrupt Multiplexing Emulation Considerations Power ManagementEmulation Control Emac Control Module Registers Acronym Register Description Offset Acronym Register Description Emac Control Module Revision ID Register RevidBit Field Value Description Emac Control Module Software Reset Register Softreset Reset Intprescale Emac Control Module Interrupt Control Register IntcontrolC2TXPACEEN Bit Field RXCH7EN TXCH7EN Statpenden Hostpenden LINKINT0EN USERINT0EN Statpenden RXCH5THRESHSTAT RXCH7THRESHSTATRXCH6THRESHSTAT RXCH4THRESHSTAT RXCH7STAT TXCH7STAT LINKINT0STAT StatpendstatHostpendstat USERINT0STAT Rximax Allowemacinterrupts Tximax Management Data Input/Output Mdio Registers Mdio Revision ID Register RevidMdio Revision ID Register Revid Field Descriptions Mdio Control Register Control Mdio Control Register Control Field Descriptions PHY Acknowledge Status Register Alive Field Descriptions PHY Acknowledge Status Register AlivePHY Link Status Register Link PHY Link Status Register Link Field Descriptions USERPHY1 USERPHY0 USERPHY1 Writing a 0 has no effect USERACCESS1 USERACCESS0 Effect W1S-0 Mdio User Command Complete Interrupt Mask Clear Register Userintmaskclear Mdio User Access Register 0 USERACCESS0 Mdio User Access Register 0 USERACCESS0 Field Descriptions Phyadrmon Mdio User PHY Select Register 0 USERPHYSEL0Linksel Linkintenb Linksel Mdio User Access Register 1 USERACCESS1 Mdio User Access Register 1 USERACCESS1 Field Descriptions Mdio User PHY Select Register 1 USERPHYSEL1 Mdio User PHY Select Register 1 USERPHYSEL1 Ethernet Media Access Controller Emac Registers Emcontrol MacconfigMacstatus Fifocontrol Network Statistics Registers Transmit Revision ID Register Txrevid Field Descriptions Transmit Revision ID Register TxrevidTransmit Control Register Txcontrol Transmit Control Register Txcontrol Field Descriptions Transmit Teardown Register Txteardown Field Descriptions Transmit Teardown Register TxteardownTxtdnch Receive Revision ID Register Rxrevid Field Descriptions Receive Revision ID Register RxrevidReceive Control Register Rxcontrol Receive Control Register Rxcontrol Field Descriptions Receive Teardown Register Rxteardown Field Descriptions Receive Teardown Register RxteardownRxtdnch Transmit Interrupt Status Unmasked Register Txintstatraw TX7PEND Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Status Masked Register Txintstatmasked Transmit Interrupt Mask Set Register Txintmaskset TX7MASK Transmit Interrupt Mask Clear Register Txintmaskclear Transmit Interrupt Mask Clear Register Txintmaskclear Statpend MAC Input Vector Register MacinvectorMAC Input Vector Register Macinvector Field Descriptions RX0THRESHPEND MAC End Of Interrupt Vector Register Maceoivector Intvect Receive Interrupt Status Unmasked Register Rxintstatraw Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Status Masked Register Rxintstatmasked Receive Interrupt Mask Set Register Rxintmaskset Receive Interrupt Mask Clear Register Rxintmaskclear Receive Interrupt Mask Clear Register Rxintmaskclear MAC Interrupt Status Masked Register Macintstatmasked MAC Interrupt Status Unmasked Register MacintstatrawHostpend Statpend Hostmask Statmask MAC Interrupt Mask Set Register MacintmasksetMAC Interrupt Mask Clear Register Macintmaskclear Hostmask Rxcsfen Rxcefen Rxcafen Rxpasscrc Rxqosen RxnochainRxcmfen Rxpromch Frames containing errors are filtered Receive multicast channel select Receive Unicast Enable Set Register Rxunicastset Receive Unicast Enable Set Register Rxunicastset Receive Unicast Clear Register Rxunicastclear Receive Unicast Clear Register Rxunicastclear Receive Buffer Offset Register Rxbufferoffset Receive Maximum Length Register RxmaxlenReceive Maximum Length Register Rxmaxlen Field Descriptions Receive Channel Flow Control Threshold Registers Rxfilterthresh Receive Channel n Free Buffer Count Register RXnFREEBUFFER MAC Control Register Maccontrol MAC Control Register Maccontrol Field Descriptions Loopback TxflowenRxbufferflowen Fullduplex MAC Status Register Macstatus MAC Status Register Macstatus Field Descriptions Rxqosact Emulation Control Register Emcontrol Field Descriptions Emulation Control Register EmcontrolFifo Control Register Fifocontrol Fifo Control Register Fifocontrol Field Descriptions MAC Configuration Register Macconfig Field Descriptions MAC Configuration Register MacconfigSoft Reset Register Softreset Soft Reset Register Softreset Field Descriptions MAC Source Address Low Bytes Register Macsrcaddrlo MAC Source Address High Bytes Register Macsrcaddrhi MAC Hash Address Register 1 MACHASH1 Field Descriptions MAC Hash Address Register 1 MACHASH1MAC Hash Address Register 2 MACHASH2 MAC Hash Address Register 2 MACHASH2 Field Descriptions Transmit Pacing Algorithm Test Register Tpacetest Back Off Test Register BofftestBack Off Test Register Bofftest Field Descriptions Receive Pause Timer Register Rxpause Field Descriptions Receive Pause Timer Register RxpauseTransmit Pause Timer Register Txpause Transmit Pause Timer Register Txpause Field Descriptions Valid Matchfilt Channel MACADDR0 MACADDR1 MAC Address Low Bytes Register MacaddrloMAC Address Low Bytes Register Macaddrlo Field Descriptions Valid MAC Index Register Macindex Field Descriptions MAC Address High Bytes Register MacaddrhiMAC Index Register Macindex MACADDR2 MACADDR3 MACADDR4 MACADDR5 TXnHDP Transmit Channel Completion Pointer Registers TX0CP-TX7CP Receive Channel Completion Pointer Registers RX0CP-RX7CP Broadcast Receive Frames Register Rxbcastframes Network Statistics RegistersGood Receive Frames Register Rxgoodframes Multicast Receive Frames Register Rxmcastframes Receive Alignment/Code Errors Register Rxaligncodeerrors Receive CRC Errors Register RxcrcerrorsPause Receive Frames Register Rxpauseframes Receive Undersized Frames Register Rxundersized Receive Oversized Frames Register RxoversizedReceive Jabber Frames Register Rxjabber Receive Frame Fragments Register Rxfragments Receive Octet Frames Register Rxoctets Receive QOS Filtered Frames Register RxqosfilteredGood Transmit Frames Register Txgoodframes Pause Transmit Frames Register Txpauseframes Broadcast Transmit Frames Register TxbcastframesMulticast Transmit Frames Register Txmcastframes Deferred Transmit Frames Register Txdeferred Transmit Multiple Collision Frames Register Txmulticoll Transmit Underrun Error Register TxunderrunTransmit Single Collision Frames Register Txsinglecoll Transmit Late Collision Frames Register Txlatecoll Transmit Octet Frames Register Txoctets Transmit Carrier Sense Errors Register TxcarriersenseTransmit and Receive 64 Octet Frames Register FRAME64 Network Octet Frames Register Netoctets Receive DMA Overruns Register Rxdmaoverruns Appendix a Glossary Physical Layer Definitions Term Definition Document Revision History Reference Additions/Modifications/Deletions Rfid Products ApplicationsDSP TI E2E Community Home