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5.14 Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
The receive interrupt status (masked) register (RXINTSTATMASKED) is shown in Figure 52 and described in Table 51.
Figure 52. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED)
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| Reserved |
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15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 |
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RX7THRESHPEND | RX6THRESHPEND | RX5THRESHPEND | RX4THRESHPEND | RX3THRESHPEND | RX2THRESHPEND | RX1THRESHPEND | RX0THRESHPEND |
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7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
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RX7PEND | RX6PEND | RX5PEND | RX4PEND | RX3PEND | RX2PEND | RX1PEND | RX0PEND |
LEGEND: R = Read only;
Table 51. Receive Interrupt Status (Masked) Register (RXINTSTATMASKED) Field Descriptions
Bit | Field | Value | Description |
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Reserved | 0 | Reserved | |
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15 | RX7THRESHPEND | RX7THRESHPEND masked interrupt read | |
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14 | RX6THRESHPEND | RX6THRESHPEND masked interrupt read | |
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13 | RX5THRESHPEND | RX5THRESHPEND masked interrupt read | |
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12 | RX4THRESHPEND | RX4THRESHPEND masked interrupt read | |
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11 | RX3THRESHPEND | RX3THRESHPEND masked interrupt read | |
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10 | RX2THRESHPEND | RX2THRESHPEND masked interrupt read | |
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9 | RX1THRESHPEND | RX1THRESHPEND masked interrupt read | |
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8 | RX0THRESHPEND | RX0THRESHPEND masked interrupt read | |
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7 | RX7PEND | RX7PEND masked interrupt read | |
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6 | RX6PEND | RX6PEND masked interrupt read | |
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5 | RX5PEND | RX5PEND masked interrupt read | |
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4 | RX4PEND | RX4PEND masked interrupt read | |
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3 | RX3PEND | RX3PEND masked interrupt read | |
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2 | RX2PEND | RX2PEND masked interrupt read | |
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1 | RX1PEND | RX1PEND masked interrupt read | |
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0 | RX0PEND | RX0PEND masked interrupt read | |
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SPRUFL5B | EMAC/MDIO Module | 97 |
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